Processors

Xilinx Unveils High-Performance ARM-based CPU-FPGA Hybrid Platform

Xilinx recently unveiled a new chip architecture integrating an ARM processor with an FPGA fabric. This platform centers around a dual-core ARM Cortex-A9 processor complex, including hardened memory interfaces and peripherals.  The platform architecture, shown in Figure 1, is intended to behave like a CPU first and an FPGA second.  Specifically, the CPU will boot independently—without requiring that the FPGA first be configured.  Xilinx is targeting markets that require both complex software Read more...

Analog Devices Introduces Lower-Cost SHARC Processors

Analog Devices, Inc (ADI) has announced new members of its floating-point SHARC processor family featuring lower prices and offering LQFP packages, which are easier to use in older, lower-cost manufacturing facilities. The new SHARC products target digital audio, industrial, automotive, and medical markets.  New ADSP-2147x chips feature lower power than previous SHARC products, while ADSP-2148x parts feature high performance with greater integration. These parts include on-chip memory of up to Read more...

Texas Instruments Introduces New Multi-Core System-On-Chip Architecture

TI has unveiled a new chip-level architecture for high-performance, multi-core DSP-processor-based SoCs.  Most notable among its features are new on-chip and chip-to-chip interconnection mechanisms, an upgraded high-performance DSP core, and both hardware and tools support for programming concurrent applications.  The architecture is optimized to run at 1.0 to 1.2 GHz in 40 nm process technology. According to TI, initial chips based on the new architecture will incorporate four or eight DSP Read more...

New ADI Blackfin Integrates Large Executable Flash for Control Applications

Analog Devices, Inc. (ADI) has announced new members of the Blackfin processor family targeting control-loop applications.  The new BF50x parts sport a much larger “executable” flash in place of the serial flash offered in earlier Blackfin chips, and integrate a 12-bit analog-to-digital converter suitable for control applications. Previously introduced Blackfin chips rely on serial flash memory (NAND flash using a three-wire SPI interface); data is copied by boot ROM code from the flash memory Read more...

MIPS Launches MicroMIPS Architecture with Two New Cores

This month MIPS introduced two new cores, the M14K and M14Kc, that are based on a new instruction set architecture called microMIPS.  MicroMIPS uses a mixed-width 16/32-bit instruction set to improve code density relative to the MIPS32 instruction set architecture. In general, processors with smaller program memory requirements require less on-chip and off-chip memory, and less memory bandwidth. This can translate into reduced cost and power consumption. Since cost and power are key metrics for Read more...

CEVA Simplifies DSP Software Development

This month CEVA announced significant improvements to its software tool suite.  Collectively, the new tools and features are dubbed the CEVA Application Optimizer, and are part of the CEVA-Toolbox software development suite.  CEVA describes these capabilities as providing an “end-to-end, fully C-based development flow.”  This is an important topic for users of DSP processors, who are less and less willing to write heavily target-specific C code or assembly code which requires them to become Read more...

Jeff Bier’s Impulse Response: NVIDIA GPUs Turn Up the Heat

In October of 2007, I wrote a column called “When Worlds Collide,” which was about NVIDIA’s emerging strategy of offering “general-purpose GPUs.”  At the time, I thought it was interesting that NVIDIA had begun to move beyond graphics applications to target “high-performance computing” (HPC) applications like financial and seismic analysis, thus competing with processors outside of the GPU space. I also observed that the ubiquity of GPUs in PCs would likely help NVIDIA gain traction in non- Read more...

Multicore Heats up with Chip Announcements from TI, Tilera

This month both Texas Instruments and Tilera announced new multicore chips.  TI announced the TMS320C6472, which includes six ‘C64x+ processor cores running at 500-700 MHz (depending on the family member). Tilera announced a new chip family, the TILE-Gx, which will include variants with 16-100 cores running at 1.25-1.5 GHz. The ‘C6472 is available now, while Tilera does not expect to start sampling TILE-Gx chips until late 2010. According to Tilera, TILE-Gx chips will be fabbed in a 40 nm Read more...

Quartics Announces Flexible Video Chip

This month fabless semiconductor start-up Quartics introduced the QV1721, a video coprocessor SoC targeting applications such as netbook PCs, set-top boxes and high-definition televisions.  The QV1721 is intended to be used to offload demanding video tasks from the main CPU in a system. The chip provides high-definition video encoding, decoding, and transcoding functions, along with post-processing to improve perceived video quality. Quartics recently demonstrated the QV1721 to BDTI in two Read more...

ARM Launches Cortex-A5 “Sparrow”

Last month ARM announced a 2 GHz dual-core implementation of the Cortex-A9 that targets high-performance embedded apps. This month ARM is announcing a new processor core: the Cortex-A5 “Sparrow.” Sparrow is intended for use in Internet-enabled consumer devices, particularly those with a user interface—such as cell phones, mobile audio devices, and digital picture frames. According to ARM, Sparrow is its smallest, most power-efficient Cortex core, and will initially target a 40LP process. Read more...