In February CEVA announced a new family of high-performance licensable DSP cores, the CEVA-XC family. CEVA-XC cores target 4G cellular applications, including LTE and WiMax, and are intended for use not just in handsets (as with previous CEVA cores) but also in infrastructure hardware. The CEVA-XC is an offshoot of the CEVA-X architecture (the “C” stands for communications), but the new core family is much more powerful than its predecessors. The highest-performance version supports, for
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We all know that test marketing is the best way to see if a product meets buyers’ needs. Household and consumer product manufacturers test their products with a select test market as a matter of course. They use test marketing as a rehearsal for product introduction and to avoid disasters. For technology developers and vendors, test marketing can be just as valuable, but finding the right test market can be tricky. After all, the right test market is the target market—and when this is the
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BDTI has released BDTI DSP Kernel Benchmarks™ results for the CEVA-TeakLite-III core from CEVA. As we’ve written previously, CEVA-TeakLite-III is a 32-bit DSP core that primarily targets audio applications (both portable and high-definition) but also targets VoIP and cellular baseband. It is the third generation of CEVA’s TeakLite architecture, and the first to use a native 32-bit data size. The CEVA-TeakLite-III also supports SIMD (single-instruction, multiple data) dual-16-bit MACs.
The
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BDTI has released BDTI DSP Kernel Benchmarks™ results for the SideWorks signal processing engine from CoreWorks, a Portugal-based vendor of licensable silicon intellectual property. SideWorks is a licensable DSP accelerator targeting cost and power-sensitive applications such as multimedia and communications. The core is both configurable (i.e., hardware resources included in a specific implementation are selected prior to fabrication) and reconfigurable (i.e., the movement of data and some
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BDTI has released the first independent benchmark results comparing the performance of the Sandbridge “Sandblaster” SB3500 multi-core DSP chip to that of massively parallel chips, high-performance DSP processors, and FPGAs.
Sandbridge Technologies, Inc. is a fabless semiconductor company that sells multi-core chips targeting mobile 3G and 4G baseband and multimedia processing. The SB3500 chip includes three DSP cores along with an ARM core; each of the DSP cores supports four-way
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“Connected devices” make up much of the buzz in consumer electronics these days. They are the closest thing to a “killer app” there is—but what exactly are they? All connected devices provide some sort of connection to the ‘net, many provide multimedia functionality, and more often than not, they’re for mobile use. But despite these common characteristics, connected devices span a wide range of features and functionality, from netbooks to smartphones.
Such a wide range of applications
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In the last few years, there have been a slew of massively parallel chip vendors entering the embedded processor market. The massively parallel approach has become more accepted since Intel commercialized its multi-core PC architecture. It’s still a difficult area in which to build a successful business, however, because it requires not only creating a good architecture, but also developing a sound programming model and competent development tools. Even traditional processor start-ups fail at
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ST Microelectronics recently announced a new library of digital signal processing software components for its low-cost microcontroller family, the STM32. STM32 chips are based on ARM’s Cortex-M3 core, and they target low-cost embedded applications, particularly motor control. The software component library includes a speech codec and variety of DSP and control-oriented functions, such as FIR and IIR filters, a PID controller, and an FFT. The PID controller is available in both C and assembly
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High data rates pose a number of system design challenges. They require lots of I/O and an extremely fast processor or FPGA, they need lots of memory for storage and buffering, and they eat power as data gets shipped all over the system. That’s why, when high-speed data gets to a processor, often the first thing that’s done is to compress it. But what if you could compress the data before it ever gets to the processor and before it gets shipped around the system? What if you could compress it
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On October 14, 2008, Texas Instruments introduced a high-performance multi-core DSP, the TMS320C6474 that is intended for use in computationally demanding applications such as communications infrastructure, video surveillance, and medical imaging. The chip features three 1 GHz ‘C64x+ cores, each with its own L1 data and program cache, along with 3 MBytes of aggregate (not shared) L2 cache. As shown in Figure 1, the chip also contains a Viterbi accelerator and turbo-decoding accelerator along
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