MIPS Launches MicroMIPS Architecture with Two New Cores

This month MIPS introduced two new cores, the M14K and M14Kc, that are based on a new instruction set architecture called microMIPS.  MicroMIPS uses a mixed-width 16/32-bit instruction set to improve code density relative to the MIPS32 instruction set architecture. In general, processors with smaller program memory requirements require less on-chip and off-chip memory, and less memory bandwidth. This can translate into reduced cost and power consumption. Since cost and power are key metrics for many embedded applications, 16-bit compressed instruction sets have become fairly common.

MicroMIPS is a re-encoding of the MIPS32 instruction set, with the most commonly used instructions encoded in 16 bits wherever possible. MicroMIPS also includes 15 new 32-bit instructions and 39 new 16-bit instructions.

The M14K core is a superset of the M4K core and targets a range of consumer, industrial, automotive, and office applications. Similarly, the M14Kc is a superset of the 4KEc core, and targets home entertainment, home networking, and personal entertainment applications. Both cores provide reduced interrupt latency relative to the M4K.  

The new cores include decoders for both the microMIPS and MIPS32 instruction set, so MIPS32 code need not be recompiled to run on these cores (though of course, legacy code won’t take advantage of the improved code density and new instructions).  According to MIPS, microMIPS provides 98% of the MIPS32 performance while reducing code size by 35%. 

Preliminary core characteristics for the two new cores are shown in Table 1, below. According to MIPS, the data is for worst-case conditions.

Table 1: Preliminary core characteristics

By way of comparison, the ARM Cortex-M3 is quoted on the ARM website as running at 191 MHz (worst-case), 0.31 mm², and 238 DMIPS for the speed-optimized version in 90 nm. Unlike the new MIPS cores, however, ARM has not maintained complete backwards compatibility between the Cortex-M3 and the earlier ARM7 cores, though according to ARM’s website, “substantial amounts of [ARM7] code will work on the Cortex-M3 processor without modification.”  (BDTI’s white paper comparing the DSP capabilities of the Cortex-M3 and MIPS M4K is available at /Services/WPAR/WhitePapers.)

The MIPS DSP Library (a set of common DSP software components, such as filters) will run on the new cores since they support the MIPS32 instruction set, but the library has not yet been ported to microMIPS.

MicroMIPS is not MIPS’ first compressed instruction set; the company offered the MIPS16e 16-bit instruction set with earlier cores. According to MIPS, MIPS16e sacrifices performance to enable code compression, while the newer microMIPS doesn’t take the same performance hit. Nothing comes for free, however, and the price of microMIPS is that it reduces the maximum core frequency by about 10% relative to the same core without microMIPS. Another key difference between the two compressed instruction sets is that MIPS16e supports only a subset of the MIPS32 instruction set architecture, while microMIPS supports the full instruction set.

The M14K and M14Kc will be available as beta releases for “early access” customers in December 2009, and generally available in February 2010.