BDTI recently completed an in-depth analysis of FPGAs’ suitability for DSP applications. We found that, in some high-performance signal processing applications, FPGAs have several significant advantages over high-end DSP processors. Our recent benchmark results (shown in Figure 1), for example, have shown that high-end, DSP-oriented FPGAs have a huge throughput advantage over high-performance DSP processors for certain types of signal processing. And FPGAs, which are not constrained by a
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This month BDTI and silicon intellectual property licensor ARC International announced completion of BDTI Solution Certification™ of the H.264 video decode performance of the ARC Video Subsystem. The ARC Video Subsystem, the first product to be certified under BDTI’s Solution Certification Service, is a programmable subsystem capable of supporting multiple video standards. In certifying the solution, BDTI has independently verified its performance using proprietary BDTI bitstreams and
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Stream Processors, Inc. (SPI) this week unveiled its data-parallel processor architecture and announced two chips based on the architecture. According to SPI, its architecture is optimized for compute-intensive embedded applications which exhibit a high degree of data parallelism, such as video and imaging. SPI believes that cost-performance and developer productivity advantages will enable its chips to compete successfully against FPGAs, high-end DSPs, and ASICs in these applications.
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Algorithms are the essence of digital signal processing; they are the mathematical “recipes” that transform signals in useful ways. Companies developing new DSP algorithms, or considering purchasing or licensing algorithms, often need to assess whether the algorithm will fit within their processing budget–and thereby within their cost and power consumption targets.
But estimating an algorithm’s processing load can be difficult if the algorithm has not already been carefully mapped onto
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At the Consumer Electronics Show last month I was struck (not for the first time) by the number of consumer electronics products that rely on digital signal processing—at this point, nearly all of them. In fact, so many of today's products incorporate digital signal processing-based functions that it's tempting to start viewing these functions as commodities.
But in most cases, DSP functions aren't going to become commodities anytime soon. They may be ubiquitous, but they're not
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Measuring the performance of real-time digital signal processing code is essential. But whether you're using a simulator or hardware, it can be a headache to get accurate, repeatable performance measurements. In this article we'll cover some of the common pitfalls you might encounter, and present some techniques for working around them.
Why Measure?
Digital signal processing applications typically have tight speed and cost constraints, and may also have challenging real-time deadlines. In
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On January 3rd, Freescale announced the first dual-core members of its Onyx family of audio DSPs. The first two chips in the family, the DSP56720 and DSP56721, feature two DSP5636x cores operating at 200 MHz. The chips mainly target high-definition audio processing in next-generation DVD players. To this end, Freescale offers DSP5636x software implementing audio decoders supported by the HD-DVD and Blue-Ray standards, including Dolby Digital+, Dolby TrueHD, and DTS-HD. In addition to DVD
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In December Texas Instruments announced the TCI6487 multi-core baseband processor. The device will be manufactured in a 65 nm process and is intended mainly for GSM, TD-SCDMA and WiMAX basestation applications.
The TCI6487 features three TMS320C64x+ DSP cores running at 1 GHz. In comparison, its predecessor, the TCI6482, featured a single 1 GHz ‘64x+ core. TI has also added an antenna interface supporting OBSAI and CPRI protocols.
DSP cores in the TCI6487 communicate with each other and
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Multithreaded programming isn't a new idea, but it's currently experiencing a major upswing in attention. That's because many multi-core chip vendors are currently pushing multithreading as the best way to harness their chips' processing horsepower.
But a recent influential paper by Dr. Edward Lee argues that multi-threaded application programming, as commonly practiced, is a flawed methodology that invites a range of nasty, hard-to-identify bugs.
Dr. Lee is a professor of EECS at UC
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Compiling digital signal processing application code is not a push-button process—at least, not unless you're willing to settle for inefficient code. Signal processing algorithms (and the processors commonly used to run them) have specialized characteristics, and compilers usually can't generate efficient code for them without some level of programmer intervention.
Learning how to coax efficient signal processing object code out of a compiler is an important skill, and can reduce (or eliminate
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