As multimedia systems grow in complexity, system and SoC developers are increasingly relying on vendors to provide “solutions”—combinations of hardware and software that implement complete multimedia functions such as audio and video compression and decompression. Vendors have responded by offering a growing number of such solutions.
This has created a new challenge for system and SoC developers: vendors’ claims regarding the functionality and performance of their solutions are difficult
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BDTI has released the first independent benchmark results comparing the performance of picoChip’s massively parallel PC102 chip to that of high-performance DSP processors and FPGAs.
picoChip is a fabless semiconductor company that sells multi-core chips for wireless infrastructure applications, such as WiMax base stations. The PC102 is based on picoChip’s multiple-instruction, multiple-data (MIMD) architecture and contains 308 heterogeneous processor cores and 14 co-processors, all of which
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Back in 2001 I wrote a column about the merits of using heterogeneous designs for signal processing-oriented applications. My argument went like this: signal processing applications typically encompass diverse data rates, data types, and algorithms, and it often makes sense to address these needs using a collection of similarly diverse processing engines rather than taking a one-size-must-fit-all approach. Back then, using a heterogeneous processing architecture usually meant using two or
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The number of vendors offering massively parallel processors for digital signal processing is growing. As independent technology analysis company BDTI explained in its earlier article, there are a wide range of architectural approaches, each with unique pros and cons. Regardless of the approach taken, these chips are all highly complex, and they all face a similar challenge: making it easier for users to get their applications up and running. In this article BDTI will discuss some of the new
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Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1. (The middle of the family range is filled out by the AV 404V, AV 406V, and AV 407V) are intended for compression-centric applications such as camera phones, portable media players,
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Pretty much everyone agrees that digital video has become a killer app for embedded processing engines. But “video” can mean different things to different people; the term encompasses a diverse set of applications with very different requirements. A processor you’d use for video playback in a low-cost cell phone, for example, isn’t going to cut it for an HDTV set and vice versa.
System developers and their chip suppliers must understand exactly what kinds of video they need to handle, and
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Digital video compression/decompression algorithms (codecs) are at the heart of many modern video products, from DVD players to multimedia jukeboxes to video-capable cell phones. Understanding the operation of video compression algorithms is essential for developers of the systems, processors, and tools that target video applications. In this article, we explain the operation and characteristics of video codecs and the demands codecs make on processors. We also explain how codecs differ from
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Tensilica is now offering a high-performance licensable video engine capable of MPEG-4 ASP encoding at D1 resolution. The processor is called the Diamond 388VDO, and it’s one of four new dual-core “VDO” video engines from Tensilica. The 388VDO is the highest-performance member of the quartet and supports a variety of video codec standards at resolutions up to D1 (i.e., standard definition television). Target applications include chips for mobile handsets and personal media players.
In its
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In June Atmel announced the Customizable Atmel Processor (CAP), a family of customizable microcontrollers, and two initial devices. Customization in the CAP is achieved via a gate array block in which users can implement functions ranging from processor cores and peripherals to algorithm accelerators. Atmel intends the CAP devices to be used in industrial, consumer, medical, and automotive applications, as replacements for the microcontroller-FPGA combinations often used in these applications
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Processor designers, marketers, and users with a sophisticated understanding of benchmarks know that raw benchmark results rarely give the most accurate picture of processor performance for a specific application scenario. While useful for providing a general impression of processor capabilities, raw benchmark results must be adapted to give a clear sense of how processors will perform in a particular application.
For example, one large manufacturer of wireless equipment relies on BDTI
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