Editor’s Note: This article contains selected highlights from BDTI’s new report, FPGAs for DSP, Second Edition.
In recent years, FPGAs (field-programmable gate arrays) have become increasingly attractive as signal processing engines, sometimes used alone and sometimes in conjunction with a processor chip. The largest FPGA vendors, Altera and Xilinx, have invested heavily in developing DSP-oriented chips and development tools. BDTI has just completed an in-depth study of these DSP-oriented
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BDTI has released independent benchmark results for the ARM1176 licensable processor core on the BDTI DSP Kernel Benchmarks™, which measure overall signal-processing performance, and the BDTI Video Decoder Benchmark™, which measures performance on video decoding and similar workloads.
Based on its results on the BDTI DSP Kernel Benchmarks™, the ARM1176 achieves a BDTImark2000™ score of 1200 at a clock rate of 335 MHz (All processor core performance data in this article assumes use of the
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Many DSP-oriented systems are composed of multiple application tasks—e.g., an audio codec, a video codec, and a networking stack. During initial product development, the system designer typically divvies up the available processor MIPS among the tasks, and assigns the tasks to various engineering teams. These teams then go off to craft their code to stay within the MIPS they've been allocated. When all of the components are finished, the tasks are integrated together and the system designer
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Today fabless chip start-up Sandbridge announced its new SB3011 chip, a low-power derivative of the SB3010 chip announced in July 2005. The chip is fully programmable and is aimed at replacing baseband and application processors in cellular handsets. Sandbridge will face stiff competition from dominant players such as TI and Qualcomm that have close relationships with handset manufacturers, but the company remains optimistic; the company recently received $15.4 million in Series B funding
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On September 9th, silicon intellectual property licensor ARC made two related announcements: It unveiled a new configurable multimedia player subsystem based on its ARC600 family of cores, and announced a new partnership with Chinese silicon foundry Semiconductor Manufacturing International Corp. (SMIC). Under ARC's agreement with SMIC, ARC licensees that design chips in China and use SMIC for fabrication will pay no up-front licensing fees, paying royalties only when their chips start
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While nearly all signal processing applications require some degree of software optimization, some applications require a sophisticated, multi-tiered optimization approach in order to meet their performance goals.
To obtain the most efficient code, DSP software must be optimized at four distinct levels. First, the software architecture and data flow must be designed to take maximum advantage of the processor’s resources. Second, the appropriate data types must be selected—too big and you’
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I have two ways of looking at processors. If I’m in geeky-engineer mode, I’m thrilled to learn about the hard-core technical details—like how the branch prediction works, and why the DMA engine is breathtaking in its sophistication and complexity, and how the chip uses a revolutionary new method for implementing… whatever.
But if I’m in product-development mode and I have to choose a processor, the last thing I want to hear is how complicated it is. No, I want to hear how straightforward
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Nearly everyone who works with embedded processors relies on benchmark results in one way or another. Executives use them to help make critical business and technical decisions. Engineers and managers use them to evaluate in-house processors or to help choose a processor for a new product. Marketers use them for competitive analysis and to add credibility to their marketing programs.
Good benchmarks, used properly, are an invaluable tool for all of these purposes. Unfortunately, there are
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On August 21st fabless semiconductor startup Ambric unveiled its massively parallel processor architecture. Ambric joins a host of start-ups pursuing a similar idea: chaining together a large number of simple RISC-like processor cores in ways intended to avoid inter-processor communication bottlenecks and programming problems found in traditional multiprocessor systems. In the Ambric architecture, individual processors can run at different clock speeds, and processors operate asynchronously
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Say you’re looking for an H.264 video decoder solution to integrate into your system, and you’re trying to compare what's available. You figure this should be a straightforward process–after all, H.264 is a standards-based codec, so it should be easy to find apples-to-apples performance data.
You confidently search the Internet and are rewarded with a bunch of performance data. But (as is true with any multimedia solution) the format and type of data is all over the map. For example
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