TI has unveiled a new chip-level architecture for high-performance, multi-core DSP-processor-based SoCs. Most notable among its features are new on-chip and chip-to-chip interconnection mechanisms, an upgraded high-performance DSP core, and both hardware and tools support for programming concurrent applications. The architecture is optimized to run at 1.0 to 1.2 GHz in 40 nm process technology.
According to TI, initial chips based on the new architecture will incorporate four or eight DSP
Read more...
Analog Devices, Inc. (ADI) has announced new members of the Blackfin processor family targeting control-loop applications. The new BF50x parts sport a much larger “executable” flash in place of the serial flash offered in earlier Blackfin chips, and integrate a 12-bit analog-to-digital converter suitable for control applications.
Previously introduced Blackfin chips rely on serial flash memory (NAND flash using a three-wire SPI interface); data is copied by boot ROM code from the flash memory
Read more...
It’s a tough world out there for small processor companies. It’s tough to attract new customers, and tough to support the ones you manage to get. A key challenge is the trend towards customers consolidating their purchasing: many system companies prefer to use fewer unique processors in their systems, for both business and technical reasons. From a business standpoint, using fewer different processors (and thus, using fewer vendors) can help streamline procurement and provide negotiating
Read more...
Although the economy appears to be on the mend, established technology companies and venture capitalists alike remain cautious about their investments. When considering investments, acquisitions or major product purchase decisions, they are wary of accepting companies’ claims about their technology at face value and often turn to outside experts for technical due diligence evaluations to assess and manage risk.
Technical due diligence can encompass a broad-based evaluation of the value of
Read more...
This month MIPS introduced two new cores, the M14K and M14Kc, that are based on a new instruction set architecture called microMIPS. MicroMIPS uses a mixed-width 16/32-bit instruction set to improve code density relative to the MIPS32 instruction set architecture. In general, processors with smaller program memory requirements require less on-chip and off-chip memory, and less memory bandwidth. This can translate into reduced cost and power consumption. Since cost and power are key metrics for
Read more...
This month CEVA announced significant improvements to its software tool suite. Collectively, the new tools and features are dubbed the CEVA Application Optimizer, and are part of the CEVA-Toolbox software development suite. CEVA describes these capabilities as providing an “end-to-end, fully C-based development flow.” This is an important topic for users of DSP processors, who are less and less willing to write heavily target-specific C code or assembly code which requires them to become
Read more...
In October of 2007, I wrote a column called “When Worlds Collide,” which was about NVIDIA’s emerging strategy of offering “general-purpose GPUs.” At the time, I thought it was interesting that NVIDIA had begun to move beyond graphics applications to target “high-performance computing” (HPC) applications like financial and seismic analysis, thus competing with processors outside of the GPU space. I also observed that the ubiquity of GPUs in PCs would likely help NVIDIA gain traction in non-
Read more...
Energy consumption is a chief concern for most embedded applications, especially for portable applications where battery life is paramount. In these applications, an accurate understanding of energy consumption is critical to processor selection and to system design. Unfortunately, many obstacles hinder comparisons of processors’ energy consumption.
One key problem is that processor vendors usually report power consumption, not energy consumption. Calculating energy consumption—which is
Read more...
This month both Texas Instruments and Tilera announced new multicore chips. TI announced the TMS320C6472, which includes six ‘C64x+ processor cores running at 500-700 MHz (depending on the family member). Tilera announced a new chip family, the TILE-Gx, which will include variants with 16-100 cores running at 1.25-1.5 GHz. The ‘C6472 is available now, while Tilera does not expect to start sampling TILE-Gx chips until late 2010. According to Tilera, TILE-Gx chips will be fabbed in a 40 nm
Read more...
This month fabless semiconductor start-up Quartics introduced the QV1721, a video coprocessor SoC targeting applications such as netbook PCs, set-top boxes and high-definition televisions. The QV1721 is intended to be used to offload demanding video tasks from the main CPU in a system. The chip provides high-definition video encoding, decoding, and transcoding functions, along with post-processing to improve perceived video quality.
Quartics recently demonstrated the QV1721 to BDTI in two
Read more...