Lately, neural network algorithms have been gaining prominence in computer vision and other fields where there's a need to extract insights based on ambiguous data.
As I wrote last year, classical computer vision algorithms typically attempt to identify objects by first detecting small features, then finding collections of these small features to identify larger features, and then reasoning about these larger features to deduce the presence and location of an object of interest (such as a face
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The SHARC DSP family has long been a design staple of mid-range and high-end audio, industrial and other digital signal-processing intensive applications. With its two new series of products, Analog Devices delivers dual-core SHARC to the market for the first time. And the ADSP-SC58x devices also integrate an ARM processor core to tackle system control code functions (Figure 1).
Figure 1. A migration from the 65 nm to 40 nm process node enables a high degree of integration in Analog Devices'
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Practical computer vision (i.e. "embedded vision") is rapidly becoming a mainstream reality. Numerous processor chip and core suppliers have responded to increasing market demand with a variety of processor options. One of the first companies to target the vision processor space, Quebec, Canada-based CogniVue, has just unveiled its third-generation core architecture.
CogniVue's path to the vision market involved several intermediate steps. The company was initially founded fifteen years ago by
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BDTI is well known for its software-related capabilities: performance- and power consumption-related benchmarking, for example, along with algorithm evaluation and development and optimization work. In such projects, BDTI frequently employs semiconductor manufacturers' evaluation boards and associated software toolsets, which are often combined to create development kits. And as noted several months ago, BDTI is no stranger to hardware development, either, partnering with chip suppliers to co-
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Back in early 2010, Xilinx first began discussing its "Extensible Processing Platform" concept, followed by a formal introduction of the Zynq-7000 product family one year later (with initial sampling another year after that). Zynq-7000 wasn't the first processor-plus-programmable logic combo chip; both Xilinx and competitors like Altera had previously developed such devices. But at the time it was unique in that it embedded a full-fledged processor subsystem, including a full peripheral set,
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Portable electronics devices are incorporating increasingly sophisticated multimedia capabilities, while at the same time striving to meet tough size, weight, battery life and cost requirements. Recently, a BDTI client launched a design for a new portable multimedia system requiring billions of floating-point operations per second and low input-to-output latency, and single-digit power consumption to enable compact and fan-less system operation. Robust software development tools were also a key
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At January's CES (Consumer Electronics Show), Cadence showed that has picked up the baton and continued the pace of acquired company Tensilica by announcing the eleventh generation of the Xtensa configurable processor architecture. First unveiled in 1999, Xtensa has received evolutionary advancements on a roughly two year cycle since that time; in late 2013, for example, InsideDSP covered the Xtensa 10 product release. At the time, Cadence had also unveiled the fifth generation of its LX
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Massively parallel processor supplier Tilera is a company that InsideDSP has kept an eye on for nearly a decade now, stretching back to BDTI's benchmarking of the company's first-generation TILE architecture in its 64-core form (see sidebar "Company, Architecture and Product Line Background"). After an initial flurry of product releases, privately held Tilera grew uncharacteristically quiet over the next half-decade, focusing on rolling out the remainder of the TILE-Gx family, conserving its
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As applications become more complex, and processors become more powerful, system developers increasingly rely on off-the-shelf software components to enable rapid and efficient application development. This is particularly true in digital signal processing, where application developers expect to have access to libraries of optimized building-block functions to speed their work.
A leading SoC developer recently contracted BDTI to assist it in developing a comprehensive library of software
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Emerging and evolving options for high-level design of FPGAs is a topic of ongoing interest at InsideDSP. Recently, for example, BDTI covered the latest version of Calypto's Catapult C-based design environment. Similarly, in August 2012 InsideDSP discussed the C-based high-level synthesis (HLS) facilities that Xilinx bundled in some versions of its Vivado FPGA design toolset. And less than a year ago, BDTI analyzed a different approach to high-level synthesis, based on the Khronos Group's
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