Back in early 2010, Xilinx first began discussing its "Extensible Processing Platform" concept, followed by a formal introduction of the Zynq-7000 product family one year later (with initial sampling another year after that). Zynq-7000 wasn't the first processor-plus-programmable logic combo chip; both Xilinx and competitors like Altera had previously developed such devices. But at the time it was unique in that it embedded a full-fledged processor subsystem, including a full peripheral set, enabling the chip to operate even without a configuration bitstream loaded in the FPGA portion.
The four-member Zynq-7000 product family integrated a dual-core ARM Cortex-A9 CPU running at 800 MHz, and was fabricated on TSMC's 28 nm process (other higher density, FPGA-only products from Xilinx leveraged TMSC's more advanced 20 nm process). The combination of processor plus FPGA on a single chip is intriguing for many applications, where the FPGA fabric can be used to provide additional I/O interfaces for the processor, and also to implement specialized co-processors to offload demanding tasks from the CPU. Utilizing the FPGA in the Zynq-7000 family, though, was initially a somewhat cumbersome process, not particularly amenable to software engineers. While software development targeting the ARM CPU leveraged a conventional tool flow, the FPGA design (often implementing hardware-accelerated portions of the software algorithms) mainly relied on conventional register-transfer-level logic design.
The situation began to shift in a software-developer-friendly direction in mid-2012, when Xilinx's revamped Vivado FPGA toolset integrated the high level synthesis (HLS) tool derived from the company's acquisition of start-up AutoESL and its AutoPilot product line (PDF). HLS had previously been available standalone from Xilinx for around $10,000; now it was bundled within the sub-$5,000 Vivado System Edition version. But, while the ARM firmware and FPGA hardware could now both be developed using C or C++, the design flows and tools used in them were still distinct (Table 1).
Table 1. Xilinx's new SDSoC toolset significantly expands capabilities versus prior C/C++ offerings.
With the more recently release of Xilinx's SDx toolsets, Xilinx is making it more feasible for software developers to target FPGAs (Figure 1). First, in March 2014, came SDNet, targeting networking applications and intended as a high-level specification environment for software-defined data plane programming. Toward the end of 2014 it was joined by SDAccel, which focused on datacenter designs historically dominated by CPUs and GPUs and provided an OpenCL, C and C++ environment intended to deliver a familiar programming experience for devleopers targeting FPGA-based accelerators.
Figure 1. SDSoC is the third member of a family of FPGA development tools tailored for software engineers.
And now the third member of the SDx family is public (Figure 2). SDSoC targets general-purpose embedded designs; its C and C++ environment is intended to deliver a familiar programming experience for software engineers and platform developers. As the flowchart shows, SDSoC enables an iterative design flow in which the developer selectively migrates portions of the application code to the FPGA, obtaining estimated latency, throughput, power consumption, and resource utilization results achieving the desired balance between software and accelerated hardware, at which point compilation finalizes both the FPGA bitmap and the software image.
Figure 2. SDSoC enables you to iterate your design until the hardware-versus-software balance is optimal; only then do the compilation, FPGA place-and-route, and other more time-consuming steps need to occur.
SDSoC supports the Zynq-7000 family, but Xilinx has also just announced its next-generation CPU-FPGA hybrid, which is one of the three product families to be based on TSMC's 16 nm "FinFET" 3D transistor process (Figure 3). As seen in the block diagram, the company's made good use of the additional transistor budget available courtesy of the more advanced lithography, therefore rationalizing the naming change from "SoC" to "MPSoC". The host CPU moves from a dual-core 32-bit ARM Cortex-A9 to a quad-core 64-bit Cortex-A53, for example, and is joined by a 32-bit dual-core Cortex-R5. And a full-blown graphics processor core is now onboard as well; unfortunately, the ARM Mali-400MP is not capable of GPGPU (i.e. GPU Compute) usage, although in fairness the FPGA partition is an equivalent if not superior acceleration resource.
Figure 3. Although SDSoC is intended to work well with Xilinx's legacy Zynq-7000 products, it is also optimized for the company's upcoming "UltraScale+ MPSoC" Zynq devices, which will deliver substantial increases in hardware resources.
Xilinx projects that the Zynq UltraScale+ MPSoC family will deliver substantially improved performance and energy efficiency versus its Zynq-7000 predecessor in common applications, although the older product line will continue to be supported and will remain the more cost-effective option for modest-performance system designs (Figure 4). Xilinx's SDSoC toolset is now available in "early access" form for key customers (some of whom have been working on designs using it since mid-2014), and is scheduled to transition to broader "public access" status in June, along with an expanded suite of optimized library functions.
Figure 4. Initial benchmark projections from Xilinx show significant performance and energy efficiency gains for newer Zynq MPSoC products, although Zynq-7000 devices will be more cost effective for modest-performance applications.
As for Xilinx's 16 nm UltraScale+ products, which include the next-generation Zynq MPSoC, their design tools are now available to strategic customers, broadening to "early access" next quarter. The first chip tape-out is also forecast to occur next quarter, with initial product samples slated to ship to lead customers by the end of the year. Xilinx's Zynq family has long been a case study of exciting potential hampered to some degree by a lack of tools enabling software developers to easily harness the FPGA fabric. SDSoC aims to address these tool shortcomings, while the new UltraScale+ MPSoC family boosts the appeal of Xilinx’s heterogeneous processor chips for demanding applications.
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