High-level synthesis tools (i.e., tools that take high-level language code and generate an RTL-based hardware implementation) have been around a long time, but historically they have had limited success in the market. The primary problems have been that they have been hard to use and have generated relatively inefficient implementations. But their potential advantages are compelling, particularly as applications become more complicated: in the best case they can reduce implementation time
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In February when Xilinx announced its new Virtex-6 and Spartan-6 families, the company also discussed its intention to provide more domain-oriented development tools and development paradigms. In April the company began to make good on its promise by announcing domain-specific tool bundles as part of its new release of the ISE Design Suite, Rev 11.1.
The new suite comprises four “editions” of the tools: logic, digital signal processing, embedded processing, and system-level design. Each
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Time-to-market pressures mean that system designers, software developers and integrators require more than just hardware from their chip vendors. They demand reliable, easy-to-use software development tools, OS support, middleware and application software components, I/O support, and more—right out of the box. To win design-ins, a chip vendor must deliver much more than just processing performance on a board. Vendors are responding to this demand by packaging development boards, software
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Whenever I talk to chip and tool vendors about the ease-of-use of their products, they invariably brag about how much time they’ve invested in ensuring a good “out-of-the-box experience.” What they mean is that, when a customer first starts using one of their products (say, a development kit), the customer finds it easy to get the tool up and running. This is important, and it’s hard to do well. We here at BDTI often run into glitches in this area: things like missing files, documentation
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We all know that test marketing is the best way to see if a product meets buyers’ needs. Household and consumer product manufacturers test their products with a select test market as a matter of course. They use test marketing as a rehearsal for product introduction and to avoid disasters. For technology developers and vendors, test marketing can be just as valuable, but finding the right test market can be tricky. After all, the right test market is the target market—and when this is the
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When is the right time to adopt a new way of doing things? It’s a no-brainer that systems designers have to select a new tool or component when the one they’ve been using is obsoleted. But should a company adopt a new design methodology when the one they’re using still works? After all, “if it ain’t broke, don’t fix it”—right? Well, maybe.
Established signal processing system design techniques are bending under the pressure of increasing integration, greater application complexity,
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As computational requirements go up and fab processes increasingly bump up against inconvenient physical limitations, multicore solutions are becoming more attractive. The problem is that no one wants to program them, because there are lots of challenges associated with implementing applications on multiple cores. One challenge lies in handling inter-core communications. How will cores with different data formats, different interconnects, and different OS’s exchange data and talk to each
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At NI Week in August, National Instruments introduced a new product line, a set of eight boards that are intended as complete, off-the-shelf computing-plus-I/O solutions for medical, mechatronic, and industrial applications, among others. The boards are called “Single-Board RIOs” (RIO is short for “reconfigurable I/O”), and each board contains a PowerPC CPU, a Xilinx Spartan FPGA, and analog and digital I/O. The I/O channels are connected to the FPGA, enabling the user to customize timing and
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An attractive attribute of licensable processor cores is the flexibility chip designers have to adapt these cores to their chosen fabrication process, cell library, tool flow, logic synthesis goals and other conditions. In other words, chip designers can tune the core to the needs of a particular application and to their preferred chip design methodology. An unfortunate side effect of this flexibility is that it can be extremely difficult to make apples-to-apples comparisons between
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Fifteen years ago DSP engineers expected to write and optimize most of their software in assembly language, and they did it on DSP processors with obscure and highly specialized instruction sets. Back then, compilers for DSP processors were inefficient and couldn’t use many of the processors’ specialized performance-improving features. If you wanted to use bit-reversed addressing or circular buffers or fill delay slots, for example, you’d have to write that code yourself.
Today, most
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