This May, TI introduced its XDS560 emulator. The key new feature of this emulator is its speed: according to TI, the XDS560 supports data transfer rates of over two Mbytes per second, compared to about 20 Kbytes per second for its predecessor, the XDS510. This higher data bandwidth will be particularly useful for video-processing applications, as it will enable real-time monitoring of video data. BDTI's experience in developing video applications suggests that real-time monitoring is a rare
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ARM unveiled the ARM11, the first core to implement the ARMv6 instruction set, at the recent Embedded Processor Forum. The ARM11 contains a number of features that should prove particularly useful for DSP applications. The most prominent of these features are the new dual-16-bit multiply-accumulate (MAC) instructions. DSP algorithms typically make heavy use of MAC operations, so these instructions will likely give the ARM11 a major performance boost over its single-MAC predecessors. The ARM11
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On June 18th, Agere, Motorola, and Infineon announced that they would be teaming up to form a new company, StarCore LLC. StarCore LLC will be based on the earlier Agere/Motorola joint design center, StarCore, but with some notable differences. One difference is that, unlike the earlier alliance, StarCore LLC will be a distinct business entity separate from its parent companies. All three partners will have equal ownership in the new company, which will be headquartered in Austin, Texas. The
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At last month’s Embedded Processor Forum, Intrinsity revealed details of its MIPS32-based FastMIPS and FastMATH processors, the first processors to use Intrinsity’s “Fast14” dynamic logic technology. According to Intrinsity, Fast14 uses several novel techniques to avoid common dynamic logic problems like susceptibility to noise. Intrinsity claims Fast14 is up to three times faster than conventional static logic and backed up this claim by demonstrating a 2.2 GHz Fast14-based test chip last
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At last month’s Embedded Processor Forum, ARC described extensions to its ARCtangent customizable processor core that target VoIP applications. The extensions include enhanced saturation and rounding support for existing ALU, shifter, and multiplier operations, and new operations like absolute value and negate. These instructions are intended to improve performance on applications that conform to the bit-exact ITU and ETSI specifications for voice compression algorithms such as G.729.
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Customizable processors were all the rage at this year’s Embedded Processor Forum. Vendors from Tensilica to Toshiba touted customizable processors as the ultimate solution for DSP applications from voice-over-IP to MPEG-4 video compression. In the view of these companies, processors with fixed instruction sets are forever bound to be jacks-of-all-trades, but masters of none. A better approach, they argue, is a flexible instruction set that designers can fine-tune to do one thing well.
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In April Intel announced version 2.0 of its Integrated Performance Primitives (IPP) library of DSP functions. This library is unusual in that it supports a diverse set of processor architectures: Itanium (IA-64), Pentium 4 and Xeon (IA-32), XScale, and StrongARM. Intel claims IPP 2.0 is highly optimized for each architecture, allowing application software developers to gain the benefits of hand-optimized code without delving into architecture-specific features. IPP 2.0 uses the same function
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On Friday, April 5, DSP Group and Parthus announced the merger of DSP Group's IP licensing business with Parthus, forming a new company, ParthusCeva, Inc. According to the companies, ParthusCeva will be "the leading independent provider of DSP-based IP solutions." Many observers view the deal as another step in the inevitable consolidation of the silicon IP business, as a large number of competitors face a skittish market and seek ways to strengthen their positions.
DSP Group has been the
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TI has taken its 'C64xx family of DSPs in a new direction with its March introduction of the TMS3206411. Previously introduced 'C64xx family members are among the fastest DSPs available, but they are also among the most expensive. In contrast, the 'C6411 will emphasize cost-efficiency over raw speed: it is projected to operate at 300 MHz and will be priced at $39 in 10,000-unit quantities. The 'C6411 is also expected to be more energy-efficient than existing family members due to its
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On February 18, Analog Devices introduced a new line of mixed-signal DSPs, the ADSP-2199x. These new DSPs are based on the ADSP-219x core which contains a 16-bit data path with a single multiply-accumulate (MAC) unit. The first two members of this family, the ADSP-21990 and the ADSP-21991, target motor control applications: both include a 14-bit A/D converter, a three-phase PWM output, and other control-oriented peripherals.
With a clock speed of 160 MHz, the ADSP-2199x is one of the
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