High-level synthesis tools (i.e., tools that take high-level language code and generate an RTL-based hardware implementation) have been around a long time, but historically they have had limited success in the market. The primary problems have been that they have been hard to use and have generated relatively inefficient implementations. But their potential advantages are compelling, particularly as applications become more complicated: in the best case they can reduce implementation time
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In February when Xilinx announced its new Virtex-6 and Spartan-6 families, the company also discussed its intention to provide more domain-oriented development tools and development paradigms. In April the company began to make good on its promise by announcing domain-specific tool bundles as part of its new release of the ISE Design Suite, Rev 11.1.
The new suite comprises four “editions” of the tools: logic, digital signal processing, embedded processing, and system-level design. Each
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Xilinx recently introduced two new FPGA chip families, Spartan-6 and Virtex-6 that offer increased capacity and lower power consumption relative to their predecessors. For the first time, the new Spartan and Virtex families use the same underlying architecture to enable easier migration. There are, however, differences in fabrication process and features. Spartan-6 chips will be fabbed in a 45 nm process, while Virtex-6 chips will be fabbed in 40 nm. Spartan-6 chips incorporate DDR3
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An attractive attribute of licensable processor cores is the flexibility chip designers have to adapt these cores to their chosen fabrication process, cell library, tool flow, logic synthesis goals and other conditions. In other words, chip designers can tune the core to the needs of a particular application and to their preferred chip design methodology. An unfortunate side effect of this flexibility is that it can be extremely difficult to make apples-to-apples comparisons between
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At the end of March, Xilinx announced availability of the first two members of its Virtex-5 FXT platform, the FX30T and FX70T. The Virtex-5 FXT platform is geared towards serial communications and embedded applications, and joins three other Virtex-5 platforms: the LX, which is intended for logic-intensive applications; the LXT, which targets logic and serial communications; and the SXT, which is intended for serial communications and DSP. (The “T” in the platform name indicates that the
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Not to be outdone by rival Xilinx, Altera has made a major announcement of its own. In mid-May, Altera unveiled its next-generation high-performance FPGA family, the Stratix IV, and announced that the family will be fabbed in a 40 nm TSMC process. Xilinx beat Altera to the 65 nm node with its Virtex-5 chips, but with this announcement, it appears that Altera will leapfrog Xilinx to 40 nm—assuming that Xilinx doesn’t come out with 40 nm chips before the Stratix IV is expected to start
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Developing a new signal processing engine is expensive and risky, particularly for a small start-up or for an established company moving into an unfamiliar market. There are good reasons to take that risk: signal processing has become ubiquitous in a wide range of application areas, and offers the potential for high revenues. The flip side is that the market is already densely populated with all kinds of signal processing engines: single-core chips, multi-core chips, massively parallel
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Earlier this month, Catalytic announced that it had acquired Celoxica’s electronic system level (ESL) business. Catalytic is a start-up company that sells a MATLAB-to-C translation tool used to accelerate simulation and implementation of signal processing algorithms. Celoxica, on the other hand, developed a C-to-FPGA translation tool for creating hardware implementations of computationally demanding algorithms. Put the two tools together, and what do you get?
Potentially, you get seamless
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BDTI has released the first independent benchmark results comparing the performance of picoChip’s massively parallel PC102 chip to that of high-performance DSP processors and FPGAs.
picoChip is a fabless semiconductor company that sells multi-core chips for wireless infrastructure applications, such as WiMax base stations. The PC102 is based on picoChip’s multiple-instruction, multiple-data (MIMD) architecture and contains 308 heterogeneous processor cores and 14 co-processors, all of which
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In June Atmel announced the Customizable Atmel Processor (CAP), a family of customizable microcontrollers, and two initial devices. Customization in the CAP is achieved via a gate array block in which users can implement functions ranging from processor cores and peripherals to algorithm accelerators. Atmel intends the CAP devices to be used in industrial, consumer, medical, and automotive applications, as replacements for the microcontroller-FPGA combinations often used in these applications
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