FPGAs

Xilinx's Vivado: An "All-Programmable" Toolset for Today and Tomorrow

Over the past 25 years, programmable logic devices have grown in capacity and capability through lithography advancements and the integration of specialized functional blocks. First were dedicated memory arrays derived from the same SRAM used to build logic cells. Next came dedicated-function logic blocks such as multiply-accumulate units (MACs), to accelerate digital signal processing and other math-intensive algorithms, along with the integration of high-performance transceivers to speed Read more...

BDTI Study Validates FPGA Floating-Point Digital Signal Processing Viability, Altera Design Toolset Capabilities

In design situations where optimum performance and/or power consumption is required, implementing digital signal processing functions in dedicated hardware versus software becomes an attractive proposition. A FPGA is a particularly compelling silicon platform for realizing this aspiration, because it conceptually combines the inherent hardware attributes of an ASIC with the flexibility and time-to-market advantages of the software alternative running on a CPU, GPU or DSP. As such, FPGAs are Read more...

Xilinx Unveils “Zynq” Extensible Processing Platform Chips

In early 2010, Xilinx previewed its vision for what it calls an “extensible processing platform”—a highly integrated combination of a high-performance embedded processor subsystem and an FPGA.  Earlier this month, that vision came one step closer to reality with Xilinx’s disclosure of details of its first extensible processing platform product family.  The family, named Zynq-7000, initially comprises four chips.  Xilinx says Zynq samples will become generally available in the first half of Read more...

Xilinx Buys AutoESL, Securing High-Level Synthesis Capabilities

Xilinx has acquired high-level synthesis start-up AutoESL Design Technologies, bringing the AutoPilot high-level-synthesis tool in-house. AutoPilot accepts a C, C++, or SystemC description of the functionality of an algorithm or task and generates a register-transfer-level (RTL) implementation in Verilog or VHDL.  The RTL implementation is then processed through the traditional FPGA RTL logic synthesis, place-and-route, and verification tool flow. Like other high-level synthesis tools, Read more...

Xilinx Announces Next-Generation 28 nm FPGA Families

Xilinx recently announced its next-generation “7 series” FPGAs, featuring new power-saving features as well as increased capacity and performance.  The series will be composed of three chip families, all fabricated in TSMC’s high-k metal gate (HKMG) 28 nm technology.  All three families will use the same logic cells, block RAMs, DSP slices, and I/O cells.  Compared to existing 40 nm Xilinx devices, Xilinx claims that, in typical applications, the new FPGAs will reduce power consumption by 50, Read more...

Altera Announces Variable-Precision DSP Blocks in Stratix V FPGAs

Altera recently disclosed architecture details of its next generation Stratix V FPGA family.  The architecture features a variable-precision DSP block, designed to provide better resource utilization for algorithms requiring a variety of data widths.  Altera represents this approach via a variable precision “dial,” shown in Figure 1.  In addition to 18-bit by 18-bit (18×18) and 36×36 modes supported by previous blocks, the DSP block natively supports three 9×9 multiply operations or one 18×25 Read more...

Xilinx Unveils High-Performance ARM-based CPU-FPGA Hybrid Platform

Xilinx recently unveiled a new chip architecture integrating an ARM processor with an FPGA fabric. This platform centers around a dual-core ARM Cortex-A9 processor complex, including hardened memory interfaces and peripherals.  The platform architecture, shown in Figure 1, is intended to behave like a CPU first and an FPGA second.  Specifically, the CPU will boot independently—without requiring that the FPGA first be configured.  Xilinx is targeting markets that require both complex software Read more...

Synfora’s PICO High-Level Synthesis Tool Achieves BDTI Certification

BDTI recently completed an in-depth evaluation of Synfora’s PICO tool through the BDTI High-Level Synthesis Tool Certification Program™.  BDTI evaluated the process of implementing applications on a Xilinx FPGA using PICO, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development.  PICO enabled creation of efficient FPGA implementations, with design productivity comparable to that of DSP processor software development.  The Read more...

AutoESL’s AutoPilot High-Level Synthesis Tool Achieves BDTI Certification

BDTI recently completed an in-depth analysis of AutoESL’s AutoPilot high-level synthesis tool via the BDTI High-Level Synthesis Tool Certification Program™. BDTI evaluated the process of implementing applications on a Xilinx FPGA using AutoPilot, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development. Overall, AutoPilot demonstrated a strong ability to generate high-quality RTL code—with equivalent resource utilization to hand- Read more...

BDTI Unveils High-Level Synthesis Tools Certification Program Results

This week BDTI released the first results from its High-Level Synthesis Tools Certification Program (HLSTCP).  The first tools to achieve certification are AutoESL’s AutoPilot and Synfora’s PICO.  Additional certifications will be released on an ongoing basis, as agreements with tool vendors allow.  The HLSTCP helps engineers and managers understand the capabilities of high-level synthesis (HLS) tools and assess when to consider these tools for their designs.  HLS tool vendors can use the Read more...