Texas Instruments Focuses on Low Power with New Chips

In July, Texas Instruments announced that it will offer new low-power variants of four of its key DSP processor product lines: the ’C55x, the ’C64x+, the ’C67x, and OMAP. The new family members are intended to span a wide range of low-power applications, from those that are line-powered but require low heat dissipation (such as home entertainment gear, where cooling fans are considered too noisy)  to those that require a week or more of battery life (such as portable medical monitoring devices). According to TI, there will be a total of 15 new low-power chips across the four chip families, with availability of initial chips in September; specific chips and peripherals have not yet been announced, nor has detailed pricing information. The new low-power families are listed in Table 1, below.

Table 1. TI’s new low-power chip line-up. Power notes provided by TI.

1. Power consumption assumes the DSP core is 70% loaded. It does not include power for the ’C550x's on-board FFT/FIR filter coprocessor or peripherals.
2. 70% max load of DSP core running at 300 MHz at 1.2V, mDDR 133 MHz/16 bit accessed 50% of the time, McBSP, SPI and GPIOs peripherals are active.
3. 70% max load of the DSP core  running at 300 MHz at 1.2V,  ARM core running at 300 MHz doing typical activity (peripheral configurations, other housekeeping activities); mDDR 133 MHz/16 bit accessed 50% of the time, McBSP, SPI and GPIOs peripherals are active.

TI’s low-power mainstay has been the ’C55x family, which is commonly used in portable consumer devices, for example. TI reports that the new ’C550x chips will consume 0.34 mW in standby mode and 46 mW at 100 MHz which is, according to TI, half the power of existing ’C55x devices.

The TMS320C674x chips are low-power variants of TI’s high-performance floating-point ’C67x family.  “Low-power” and “floating-point” aren’t typically used to describe the same chips; floating-point hardware is more complex and power-hungry than fixed-point hardware, and floating-point chips tend to be used in high-performance applications that aren’t particularly sensitive to energy efficiency. According to TI, however, the new chips will have power consumption ranging from 11 mW in standby mode to 420 mW when running with 70% CPU loading at 300 MHz.  The combination of relatively high processing speed and low power is intended to enable the use of floating-point math in portable applications—such as high-end portable audio equipment.  According to TI, pricing will start at $10 for 100-unit quantities.  (Pricing for the other chip families has not been disclosed.)

The new TMS320C640x chips are low-power variants of TI’s high-performance fixed-point ’C64x+ architecture, and according to TI they consume half the power of existing ’C64x+ chips.  Existing general-purpose ’C64x+ chips can perform eight 16-bit MACs per cycle and run at up to 1.2 GHz, though the new low-power versions top out at just 300 MHz.   The new chips target relatively high-performance, power-sensitive applications, such as software defined radios.

The OMAP-L1x chips are low-power variants of TI’s multi-core OMAP architecture. OMAP-L1x chips have an ARM9 core along with an optional DSP core, which can be either a ’C64x+ or ’C674x.  All of the cores run at 300 MHz, and according to TI, total power consumption for an OMAP-L1x chip with an ARM plus ’C674x DSP core is up to 435 mW. The OMAP-L1x chips are pin-compatible with various chips in the new ’C674x and ’C640x product lines, which should simplify migration and upgrades.

TI’s announcement is unusual in that it covers four different product lines, with a wide range of performance points. Historically TI’s DSP processor announcements have focused heavily on speed, but power is the hot new performance metric; in fact, for the most part, the new chips are slower than previous offerings.  TI is clearly staking a claim to be the low-power DSP leader, a position that will be challenged by offerings from Analog Devices’ Blackfin and SHARC families and chips based on ARM’s Cortex cores, among others.

TI says that it achieved power reductions via the use of low-leakage transistors and power management tools that support dynamic voltage and frequency scaling. In the case of the ’C550x, TI also made some modifications to the microarchitecture and instruction set, including the ability to support four independent MAC (multiply-accumulate) input operands for dual MAC computations. Previous ’C55x chips could only support three, forcing the dual MAC units to share an input. This change will improve the chip's cycle-count efficiency on some types of MAC-intensive DSP tasks and address a long-standing weakness in the architecture.  The ’C550x instruction set includes a new instruction for executing the new dual MACs—existing ’C55x code will need to be modified to take advantage of this feature.  Other changes are fairly minor; the pipeline of the new chips, for example, hasn't changed relative to earlier ’C55x chips.

A key challenge for TI—and its prospective customers—will be projecting how energy efficient the new chips will be in actual applications.  The power consumption figures provided by TI are useful as a rough guide, but typically what really matters to system developers is energy consumption, which takes into account the amount of time it takes a processor to complete a given task.  Furthermore, system designers ultimately care about overall system-level energy consumption.  A processor that appears to be more energy-efficient may require, for example, more memory accesses, which can result in a less energy efficient system. Accurately projecting energy efficiency is difficult, and system designers usually have to work with incomplete (and sometimes inaccurate) data.

In any case, TI’s new lower-power chips will likely prove welcome additions to the choices available to system designers who are under pressure to increase battery life, add features without increasing their energy budget, or reduce heat dissipation.