Freescale Introduces Basestation Baseband Accelerator

Last month Freescale introduced a new baseband accelerator chip for wireless infrastructure equipment.  The chip is tailored to the high data rates and computational demands of emerging wireless standards, including 3G-LTE, TDD-LTE, HSPA+, and WiMAX. The accelerator, called the MSBA8100, is designed to run alongside Freescale’s MSC8144, which is a high-performance quad-core DSP processor chip.  Together, the two chips are intended to provide a full baseband solution and potentially eliminate the need for FPGA- or ASIC-based acceleration.

The 90 nm MSBA8100 includes specialized hardware to accelerate turbo and Viterbi decoding (up to 120 and 85 Mbps, respectively) and various flavors of Fourier transforms, and supports rate dematching, depuncturing, and HARQ error correction. The chip also includes two RISC processors that are intended to be used as programmable interfaces between off-chip data and the on-chip accelerator hardware. The processors are responsible for pre- and post-processing, splitting tasks, and transferring data in and out of the accelerator engine. They can be programmed in C or assembly language. The chip has on-board SRAM, a DDR controller, and DMA, and supports high I/O data rates via two high-speed serial interfaces and a PCI bus interface. Freescale provides reference software for 3G-LTE and WiMAX.

Figure 1. Block diagram of MSBA8100 accelerator chip. 
(Graphic courtesy of Freescale.)

The MSC8144/MSBA8100 combo is programmed using the CodeWarrior IDE, with the MSC8144 running a device driver to provide MSC8144 applications with access to the MSBA8100. Freescale is currently offering a development board to initial customers; the board includes MSC8144 and MSBA8100 chips, along with an MPC85xx PowerQUICC III processor and serial I/O connectors.  MSAB8100 chip samples are expected by late 2008.

Freescale’s dual-chip basestation solution makes some good compromises.  Many engineers would prefer to have all the basestation processing implemented using only programmable DSP processors so they’d only have one type of processor to program and debug—but basestation processing demands are just too challenging for today’s mainstream processors.  There are a few massively parallel processors that might be able to do the trick, but these processors tend to be from relatively small companies without proven track records—or proven development tools and methodologies. (PicoChip is a notable exception here, having shipped chips for 3G cellular and WiMAX base stations for some time.) That leaves FPGAs and ASICs as the most widely used alternatives.  FPGAs are much harder to work with than programmable processors, leading to higher development costs and longer schedules. ASICs suffer from inflexibility, and have become increasingly expensive to design.  

In this context, coupling a programmable processor (the MSC8144) to an accelerator with a programmable data interface is a reasonable strategy. An open question, however, is whether the co-processor is flexible enough to adapt to changing standards, and whether the associated development tools will make this adaptation straightforward.  

Freescale’s dual-chip approach plays the middle ground between a fully homogeneous solution and a multi-technology solution (e.g., processor plus FPGA). This approach may prove attractive to system designers, though much will depend on the chip’s cost and energy efficiency—neither of which have been disclosed yet by Freescale. Freescale has also released very little specific performance information, except to say that the MSBA8100 accelerator supports up to 20 MHz 3G-LTE eNB.

For now, the MSC8144/MSBA8100 combination appears to be an interesting approach, but more concrete information is needed in order to make meaningful comparisons with the alternatives.