Note: This article has been changed on 7/18/2007 from its original version.
On May 31, CEVA Inc. announced CEVA-TeakLite‑III, a new family of DSP cores. The TeakLite‑III cores build upon CEVA’s earlier TeakLite cores, CEVA-TeakLite and CEVA-TeakLite-II, with which the TeakLite‑III is backwards compatible. To meet the precision and throughput demands of its intended applications, which include high-end audio, 3G cellular, VoIP, and portable audio players, the TeakLite‑III features support for both 32‑bit and 16‑bit fixed-point data, and increased MAC throughput relative to the earlier TeakLite cores.
The TeakLite‑III features two 16‑bit MAC units and one 32-bit MAC unit, compared to one 16-bit MAC unit in earlier TeakLite cores. It adds support for parallel execution of certain instructions, such as a MAC and some load/store instructions; and for predicated execution of instructions to accelerate decision-making code. The TeakLite‑III also features a longer pipeline, which CEVA claims will enable clock speeds of up to 350 MHz in a 90 nm process; CEVA’s earlier TeakLite cores topped out at 245 MHz. These enhancements should give the TeakLite‑III a significant edge over earlier TeakLite cores on many DSP applications. (Cited clock speeds assume a 90 nm G process and worst-case process, voltage, and temperature.) In addition, the TeakLite‑III features accelerators for Huffman coding, FFT and Viterbi algorithms. These accelerators should further boost performance of the TeakLite‑III relative to earlier TeakLite cores—CEVA’s initial performance estimates suggest a 2x boost on audio tasks, considering instruction set enhancements alone.
The TeakLite‑III will mainly compete against other audio-oriented DSP cores. For example, Tensilica’s Diamond 330HiFi Audio core features dual 24-bit MAC capability along with specialized audio instructions, and supports a variety of audio encoders and decoders. Performance estimates from Tensilica and CEVA suggest that the 330HiFi and TeakLite‑III will have similar clock speed requirements for typical audio tasks. The TeakLite‑III’s support for 32‑bit data will be attractive for some high-end audio algorithms.
Another competitor is ARC’s ARC Sound Subsystem, a subsystem specialized for audio and targeting somewhat less demanding applications compared to the TeakLite‑III. It features a RISC processor core with an FFT accelerator, and offers dual 32‑bit MAC capabilities and specialized audio instructions. The ARC Sound Subsystem supports a wide variety of audio encoders and decoders. ARC’s performance estimates suggest that the ARC Sound Subsystem may consume about 50% more clock cycles for key audio tasks relative to the TeakLite‑III and the Diamond 330HiFi. ARC also offers the ARC Sound Advanced Subsystem, a subsystem specialized for higher-end audio applications relative to the ARC Sound Subsystem; the ARC Sound Advanced Subsystem features a RISC processor core with a SIMD engine and a DMA engine.
CEVA has announced three TeakLite‑III family members: the CEVA‑TL3210, CEVA‑TL3211, and the CEVA‑TL3214. The family members come with varying assortments of L1 and L2 caches, memory management unit, and system interfaces. The CEVA‑TL3210 and the CEVA‑TL3214 are available for delivery today; the CEVA‑TL3211 will be available in early 2008.
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