At the thirteenth annual Hot Chips Conference held at Stanford University, Professor Jan Rabaey of UC Berkeley's Wireless Research Center presented an engaging tutorial on silicon platforms for next-generation wireless systems. Professor Rabaey emphasized several interesting themes in the course of his talk.
Foremost among these is the fact that modern wireless applications are becoming increasingly demanding of processors. Perhaps this is best exemplified by the increased channel coding requirements of
next-generation wireless systems. Due to the scarcity of radio
frequency bandwidth, increasingly complex coding schemes are required in order to provide the efficient spectrum use that these
next-generation systems require. And it is not only algorithms that
are more complex—data rates are also growing rapidly. The result is a tremendous increase in computation load.
According to Professor Rabaey, however, processors are not rising to
the occasion—increasing computational demands are easily outpacing increasing processor performance. The result is that processors alone are no longer sufficient to meet the demands of today's applications. Even Texas Instruments, perhaps the strongest advocate of DSP processors, validates this trend by using specialized coprocessors for channel coding—even in its fastest, most state-of-the-art products. The most efficient implementation of the heterogeneous elements required to meet modern application demands is usually an ASIC; however, developing an ASIC is expensive, time-consuming, and inherently risky. FPGAs are the ultra-flexible alternative to ASICs, but FPGA efficiency is severely compromised by the very thing that makes FPGAs flexible—configurable logic elements and interconnections that are generic.
Is there a happy medium? Professor Rabaey thinks so, and has proposed a template-based SoC design approach that combines the flexibility of an FPGA with the efficiency of an ASIC. The template-based approach is not unlike toggling a set of different options when buying a new PC—working within a general system architecture framework, one can choose various processor grades, speeds, peripherals, etc. Thus, using a template-based design approach, a system designer could create multiple chips that incorporate reconfigurable, fixed-function, and programmable elements; each chip could be configured for different functionalities. For example, from a template for wireless communication chips, a designer could build chips for cell phones, cordless phones, wireless area networks, etc. And these individual chips would themselves be reconfigurable; e.g., the cell phone chip could be configured in the field to be compatible with multiple wireless communications standards.
Add new comment