Last week LSI Logic introduced the ZSP500, the latest member of its ZSP family of superscalar DSP cores. The ZSP500 is a dual-MAC processor, but BDTI’s analysis shows that at a projected clock speed of 325 MHz, the ZSP500 will be faster on DSP tasks than many other dual-MAC processors. For example, the ZSP500 will be faster than existing members of Texas Instruments’ TMS320C55xx family or Analog Devices’ ADSP-2153x family. The ZSP500 will even outpace some quad-MAC processors like 3DSP’s SP-5. (Benchmark results for all of these processors are available at http://www.BDTI.com/Services/Benchmarks/DKB.)
The ZSP500 owes much of its impressive speed to its flexible approach to parallelism. Typical mid-range DSPs—the TMS320C55xx, for example—can execute only two instructions in parallel. These processors achieve much of their parallelism by specifying multiple operations within each instruction. This approach offers limited flexibility because instruction sets include only select combinations of operations. In contrast, the ZSP500 uses simple instructions—each of which generally specifies a single operation—and achieves its parallelism by issuing up to four instructions per clock cycle. This approach allows more flexibility in selecting operations for parallel execution.
Such flexibility is particularly important for “housekeeping” operations like initializing address registers. Housekeeping operations appear in a wide range of fairly arbitrary combinations, but it is only practical to include a few common combinations in an instruction set. Hence, it is often easier to execute housekeeping operations in parallel on the ZSP500 than on other mid-range DSPs. This is an important advantage: housekeeping tasks account for a significant portion of the workload in many applications, and the portion of processing time consumed by housekeeping tasks grows as processors apply increasing parallelism to accelerate number-crunching tasks.
While most DSPs require the programmer or compiler to identify instructions that should execute in parallel, the ZSP500 uses a superscalar architecture that automatically identifies instructions that can execute in parallel. In some ways, this makes it easier to take advantage of parallelism on the ZSP500 than on most DSPs. However, superscalar processors have their own programming challenges. For example, to make full use of the processor’s available parallelism, the programmer or compiler must anticipate the processor’s instruction-scheduling decisions and arrange instructions accordingly. And while LSI Logic’s software and tools offerings are superior to those of most DSP core vendors, they still lag significantly behind those available for the best-supported DSP chips.
BDTI recently published a report that explores these and other strengths and weaknesses of the ZSP500 in depth. Excerpts of this report are available at http://www.BDTI.com/Resources/Pubs.
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