At last month’s Embedded Processor Forum, Intrinsity revealed details of its MIPS32-based FastMIPS and FastMATH processors, the first processors to use Intrinsity’s “Fast14” dynamic logic technology. According to Intrinsity, Fast14 uses several novel techniques to avoid common dynamic logic problems like susceptibility to noise. Intrinsity claims Fast14 is up to three times faster than conventional static logic and backed up this claim by demonstrating a 2.2 GHz Fast14-based test chip last year. Intrinsity expects to make 2 GHz samples of its processors available in the fourth quarter of 2002. If Intrinsity meets this ambitious goal, its chips will have a faster clock rates than all but a few processors; by comparison, the Pentium 4 currently tops out at 2.53 GHz.
While it is easy to appreciate the benefits of a 2 GHz clock, high clock speeds do not always translate into high performance in signal-processing applications. To address the needs of these applications, the FastMATH processor includes a DSP-oriented coprocessor composed of a 4 X 4 matrix of processing elements. Each element contains an ALU, a multiply-accumulate unit, and local registers, and can communicate with other elements in the same row or column. These elements are fed by a 512-bit data bus that connects to a 1 GHz cache.
The combination of high clock speed and matrix-processing capabilities will give the FastMATH processor impressive speed, particularly on algorithms that lend themselves to high levels of parallel processing on large blocks of data. For example, Intrinsity says that on a 1024-point FFT, the 2 GHz FastMATH processor will be about six times faster than Texas Instruments’ 600 MHz TMS320C64xx and about fifteen times faster than Motorola’s 300 MHz MSC8101. If Intrinsity delivers on its claims, the FastMATH processor will be the first embedded processor to achieve this level of DSP performance—and one of the first MIPS-based processors with serious DSP capabilities. Of course, the FastMATH processor will have a smaller speed advantage on algorithms that cannot exploit its matrix-processing capabilities. BDTI is currently using the BDTI Benchmark™ suite to evaluate the performance of the FastMATH processor on a range of DSP algorithms.
Although the FastMATH processor promises impressive speed, this speed comes at the cost of high power consumption. Intrinsity projects the FastMATH processor will consume about 15 W, which is an order of magnitude higher than the power consumption of either the ’C64xx or the MSC8101. This high power consumption will be significant disadvantage, even in the infrastructure applications that the FastMATH processor targets. (Intrinsity estimates that its FastMIPS processor will consume about 10W.)
The FastMIPS and FastMATH processors are expected to be available in sample quantities in the fourth quarter of 2002; full production is planned for the third quarter of 2003. As of this writing, Intrinsity had not released pricing for its processors.
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