Last month Atmel announced the AVR32, a 32-bit microprocessor core with signal-processing-oriented features. The AVR32 targets computationally intensive, battery-powered applications such as consumer entertainment devices. Atmel plans to announce AVR32-based chips later this year; the core will also be available through Atmel’s ASIC-design services.
The AVR32 joins a growing list of 32-bit microprocessors targeting these applications. At a high level, the AVR32 is very similar to two of these microprocessors, the ARM ARM11 and MIPS MIPS32 24KE. For example, the AVR32 shares all of these features with the ARM11 (See the July 2002 DSP Insider for details):
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Single-instruction multiple-data (SIMD) techniques that enable the core to perform either two 16-bit operations or four 8-bit operations with a single instruction
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A sum-of-absolute-differences instruction that accelerates video compression
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A separate load/store pipeline
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Branch prediction with “branch folding,” a technique that reduces the branch latency to zero cycles for the most common cases
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A mixed-width 16/32-bit instruction set
Although the basic architecture of the AVR32 is similar to those of the ARM11 and 24KE, there are important differences in the details of the architectures. For example, the ARM11 and 24KE have fairly long instruction latencies. These long instruction latencies increase the difficulty of optimizing assembly-level code. BDTI has not carefully analyzed the AVR32, but an initial analysis suggests that this is less of a problem on the AVR32.
As another example, it is not possible to freely mix 16- and 32-bit instructions on many competing architectures like the 24KE. For these competitors, the processor must execute a mode change to switch between 16- and 32-bit instruction sets. In contrast, the AVR32 supports freely mixed 16- and 32-bit instructions. This difference means that the AVR32 is likely to have more compact code than many of its competitors.
Atmel has not released any information on forthcoming AVR32 chips, so it is not clear which chips the AVR32 will complete with. However, it is likely that AVR32 chips will compete with ARM- and MIPS-based chips For example, AVR32 chips will probably compete with the ARM-based Freescale i.MX family. The AVR32 chips will probably also compete with the Analog Devices Blackfin family and other media-oriented chips.
The initial AVR32 chips are expected to operate at 150 MHz, which is a relatively low clock rate for this class of processor. In comparison, competing ARM- and MIPS-based chips typically attain clock rates exceeding 250 MHz, and the Blackfin family operates at up to 750 MHz. Atmel notes that the AVR32 focuses on energy efficiency rather than top speed, but the AVR32 is likely to face tough challenges here, too. Key competitors such as the i.MX and Blackfin families are known for their energy-efficiency.
To compete successfully with these and other established competitors, AVR32 chips will need to prove that it offers competitive performance and energy efficiency—but this won’t be enough. The AVR32 chips will also need to offer a compelling mix of low cost, high on-chip integration, and solid development support such as tools and off-the-shelf software. These are challenging goals, particularly for an all-new architecture. To meet these goals, Atmel must pick the target markets for its chips carefully, and focus its product-development efforts on these markets.
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