Texas Instruments yesterday introduced four new members of its OMAP3 family of high-end application processors, and announced that these chips will be offered broadly as part of TI’s “catalog” product line.
Earlier members of the OMAP3 family were available only to selected customers of TI’s Wireless Terminal Business Unit (WTBU), typically big-name cell phone manufacturers with very high volumes. The new catalog parts are the OMAP3503, OMAP3515, OMAP3525, and OMAP3530.
Like the original OMAP3 chip (the OMAP3430, which remains exclusive to TI’s wireless handset chip division), all four of the new OMAP35xx use the ARM Cortex-A8, a superscalar 32-bit CPU core. (BDTI benchmark results are available for the Cortex-A8). The Cortex-A8 is notable for the NEON instruction set extensions intended for multimedia processing, which use a register file and execution pipeline separate from those used for the base ARM instruction set. In the OMAP35xx, the NEON SIMD instructions operate on integer and single-precision floating-point vectors up to 64 bits in length, and are appropriate for multimedia tasks such as audio and video codecs.
The OMAP3503 is sampling now with a 600 MHz Cortex-A8. (ARM claims that the Cortex-A8 can reach up to 1.1 GHz, depending on the fabrication process and layout techniques used).
Given the care with which TI laid out its implementation of the Cortex-A8 core in earlier OMAP processors, and TI’s recent announcement of an 800 MHz OMAP3440 (from TI’s WTBU), BDTI expects future OMAP35xx chips to include faster Cortex-A8 cores.
TI announced that the new OMAP3503 will be complemented by three other processors in the second half of 2008. As shown in the following table, the forthcoming family members incorporate various combinations of coprocessors to augment the ARM core.
|
Chip |
ARM Cortex- A8 |
2D/3D graphics engine |
’C64x+ DSP / video accelerator |
|
OMAP3503 |
√ |
|
|
|
OMAP3515 |
√ |
√ |
|
|
OMAP3525 |
√ |
|
√ |
|
OMAP3530 |
√ |
√ |
√ |
The figure below gives an overview of the architecture of the four chips.
The ’C64x+ in the OMAP3525 and OMAP3530 is the same DSP core found in TI DSPs such as some members of the TI DaVinci family. (BDTI has benchmarked an H.264 video decoder running on a DaVinci chip using the ’C64x+ core.) Many previously introduced members of the OMAP and DaVinci families feature an ARM processor, so the pairing of an ARM core with the ’C64x+ is not new to TI.
The video accelerators in the OMAP3525 and OMAP3530, developed by TI, are a set of dedicated hardware blocks designed to boost digital video codec performance. The dedicated hardware blocks include a motion estimator, variable length encoder/decoder, and loop filter. In addition there is a sequencer module to control the dedicated video accelerator blocks. The 2d/3d graphics accelerator in the OMAP3515 and OMAP3530 is the PowerVR SGX core from Imagination Technologies, supporting Khronos Group’s Open GL ES 2.0, an API implementing graphics for embedded systems. TI offers software modules, such as video codec implementations, that take advantage of these accelerators, and expects that most programmers will access the accelerators through an API.
In the announced OMAP35xx chips, the Cortex-A8 core is supported by a 16 kB level-1 instruction cache, a 16 kB level-1 data cache, and a 256 kB level-2 cache. In addition, 64 kB SRAM and 112 kB ROM are provided on-chip. For the ’C64x+ and video co-processors included in the other announced OMAP35xx chips, there will be separate memory blocks including cache.
Orders for the initial offering, the OMAP3503, are being taken now at $19.95 in 10K quantities; delivery is expected in four weeks.
TI’s OMAP processors as marketed by TI’s WTBU have to date been targeted almost exclusively at the wireless handset market. TI offers these new OMAP35xx for a broader class of products with wireless connectivity, video and audio capabilities. TI has not yet disclosed power consumption data. TI has likewise not yet disclosed wireless connectivity and power management chips intended for use with the OMAP35xx offering.
On-chip peripherals provided in the newly announced OMAP devices include five multichannel buffered serial ports (McBSP); four multichannel SPI ports (McSPI); four I2C interfaces; two UARTs; a UART with IRDA capability; support for various kinds of memory such as mSDRAM, LPDDR, SRAM, and pseudo SRAM; USB 2.0 HS compliant on-the-go (OTG) controllers with two additional USB host controllers; interfaces for memory stick, high-speed MultiMediaCard (MMC) and Secure Digital IO Card (SDIO); and a display subsystem with picture-in-picture (PIP), color space conversion, rotation, and resizing support. The display subsystem offers a video encoder, an LCD controller, and two 10-bit video DACs. These peripherals are appropriate for many wireless or wired multimedia products.
A major difference between the WTBU handset-oriented offerings and the new OMAP35xx is the packaging. WTBU parts typically are offered in 0.4 mm pitch packaging to meet the extreme size constraints of cell phones, and first delivery of the OMAP3503 will use the 0.4 mm pitch packaging (515-ball PBGA, 12×12 mm). But the new OMAP35xxs are also being repackaged into 0.6 mm pitch packages more suitable for general-purpose applications; these 423-ball PGBAs (16×16 mm) will be available in the second quarter of 2008. The resulting reduction in pins dictates that a few features of a few peripherals will not be available in the larger packages.
TI expects its customers to approach these devices by programming in C on the ARM core, which runs Linux and will soon run Windows CE. As discussed in an earlier InsideDSP article, TI expects the Cortex-A8 to handle general application code, and expects the ’C64x+, 2d/3d graphics accelerator, and video accelerator (when present) to handle most graphics and video tasks. While many multimedia tasks undoubtedly will be offloaded to the DSP and other coprocessors, as shown by BDTI’s benchmark results, the Cortex-A8 core with NEON has significant digital signal processing and multimedia performance. It should be noted, however, BDTI’s benchmark results are based on carefully optimized assembly code. ARM provides a vectorizing C compiler that makes use of the NEON instructions; BDTI has not yet benchmarked the compiler. The restrictions that ARM places on C code that can be easily vectorized for NEON require significant attention on the part of the programmer that ultimately limits the compiler’s ability to produce code that speeds up execution. ARM’s documentation about the performance improvement expected by using NEON with ARM’s C compiler is clear: “This means that the theoretical maximum performance for a floating-point application is a factor of four over the original scalar non vectorized code. Given typical overheads, a reasonable goal for a whole floating-point application is to aim for a 50% improvement on performance over the scalar code. For large applications that are not completely vectorizable, achieving a 25% improvement on performance over the scalar code is a reasonable goal.” Thus, it remains unclear how much the presence of NEON can be exploited without significant hand-coding (whether using assembly code or modifying C code to help the compiler).
TI is taking orders now for an evaluation module intended to support Linux and Windows CE; it contains among other peripherals a touch-screen LCD, and is expandable with a daughter card for customization by individual developers. (See BDTI’s analysis of a TI DaVinci evaluation module.)
TI states that WTBU’s OMAP offerings will remain focused on wireless handsets, the DaVinci platform will remain TI’s entry point for video applications, and the new catalog OMAP35xx chips will address products requiring a general-purpose processor and possibly video and audio capabilities. Since the four new parts are pin compatible, a designer can start with the ARM-only OMAP3503 and switch to other OMAP35xx parts as they become available.
TI made a similar introduction some years ago, adding for example the OMAP5910 and OMAP5912 to its catalog product line. Those processors, still in TI’s catalog, show overall similarity with WTBU processors such as the OMAP1610, containing an ARM9 and a ’C55x DSP co-processor. These older “catalog OMAP” parts have found some niches, but have not been adopted as widely as TI had hoped. TI believes this is due to the limited on-chip peripherals offered on these chips, and to challenges in programming these parts; TI asserts that it has overcome these challenges with the new OMAP35xx parts.
TI is the first to bring a Cortex-A8-based chip to the broad market, offering a significant boost in CPU performance over current, widely available ARM-based chips. The four announced OMAP35xx parts offer a diverse range of capabilities, with the Cortex-A8 soon to be supplemented by video and graphics coprocessors and/or a ’C64x+ DSP core. Clearly, TI is hoping that these chips will open up new markets for it in CPU-centric applications. The chips themselves offer an impressive array of capabilities. How successful they will be will most likely depend largely on how well TI has addressed users’ application development challenges.
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