Earlier this month Freescale announced that it will be offering a new six-core DSP chip, the MSC8156, that targets wireless infrastructure applications. The chip uses a new DSP processor core, the StarCore SC3850, which is similar to the earlier SC3400 but has (among other enhancements) twice the multiply-accumulate (MAC) throughput – the SC3850 can execute eight 16-bit MACs per cycle rather than four. This is the first new DSP processor product from Freescale in quite a while, and the first such product since Lisa Su took over the reigns of Freescale’s networking and multimedia group from longtime general manager
In addition to the six StarCore cores, the new chip includes Freescale’s “MAPLE-B” (“Multi Accelerator Platform Engine technology for Baseband”) hardware accelerator running at 450 MHz. This is a faster, enhanced version of the MAPLE-B accelerator used in Freescale’s baseband co-processor chip, the MSBA8100, which was announced earlier this year. The accelerator has specialized hardware to accelerate Viterbi decoding, turbo decoding, FFTs, and DFTs, along with two RISC processors to process and format incoming data, manage data buffers, and split tasks among the DSP cores and accelerators. The processors can be programmed in C or assembly.
As shown in Figure 1, the MSC8156 includes 4 Mbytes of on-chip memory (512 Kbytes for each core, plus 1 Mbyte shared between the six cores) and supports dual 64-bit DDR external memories of up to 800 MHz. It also includes a variety of high speed interfaces for serial, PCI express, and Ethernet connections.
Figure 1. MSC8156 block diagram (figure courtesy of Freescale).
The MSC8156 is intended to replace DSP-plus-FPGA combos, which was also the stated intent of Freescale’s previous two-chip offering, which comprised the MSBA8100 co-processor and the four-core MSC8144 DSP. It’s surprising that the company is announcing yet another solution in this space less than five months after introducing the MSBA8100. When asked about this, Freescale stated that it “continues to deliver the MSBA8100 (together with the ‘8144) to its customers who will deploy LTE base stations in the field during 2009.”
Freescale is emphasizing the new chip’s compatibility with earlier chips; the SC3850 is binary backwards-compatible with the SC3400 core used in the MSC8144, though code that was optimized for the SC3400 will need modifications to take advantage of new architectural features. Freescale estimates that the new core will offer an average 30% improvement boost relative to the SC3400, much of which will come from the doubled MAC throughput.
The new chip’s biggest competition will come from Texas Instruments’ multicore ‘C64x+ chips. TI dominates the wireless infrastructure baseband space, and recently announced the TMS320C6474, a multi-core chip with three 1 GHz ‘C64x+ cores plus turbo and Viterbi accelerators. TI has already announced a six-core, 600 MHz version of that chip that will be sampling in early 2009. It’s interesting to note that, unlike Freescale, TI did not choose to create hardware accelerators for FFT and DFT processing (FFTs and DFTs are used in OFDM algorithms). DSP processors like the ‘C64x and SC3850 are already designed for efficient execution of these operations, so to some extent it’s reasonable to let the processor handle these workloads. However, Freescale has taken another approach; since the transforms are both computationally demanding and algorithmically straightforward, it makes sense to offload them and free up the processor cycles.
Freescale states that it expects its new chip to offer better cost-performance and power efficiency than other solutions (including TI’s), but has not yet released any power data to back up that claim. The Freescale chip is fabbed in a 45 nm process, while TI’s is in a 65 nm process – so it’s plausible that Freescale will have a power advantage. The cost of the MSC8156 is almost certainly lower than a DSP plus FPGA combo, and appears roughly comparable to TI’s three-core chip (which sells for $225 in 1K quantities).
Add new comment