In the average American home today you will probably find ten or twenty separate digital clocks. There is one in your computer, of course, but there's probably also one on the stove, one on the VCR, one on the radio, one on your coffee machine, one on your microwave oven—your home is probably infested with them. There's a good reason for this. For products that already include an embedded processor, the addition of clock functionality comes almost for free. Just add an LCD display and a
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CMP Media and BDTI are pleased to introduce Inside[DSP], an innovative new series of periodic supplements to EE Times.
Each Inside[DSP] supplement will focus on the digital signal-processing technology behind a particular end-equipment market. These will include product categories such as consumer audio and video, mobile multimedia devices, automotive signal-processing applications, and communications equipment.
“What?” you say, “Another trade publication? Don't these guys understand that I'
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Last month ParthusCEVA, Inc. announced it would change its name to CEVA, Inc. Along with the name change, the company is shifting its focus to providing signal-processing application solutions based on its DSP cores. These moves come as part of a series of changes for the company, which was formed about a year ago by the merger of Parthus Technologies with the DSP core licensing division of DSP Group. Since the merger, the company has moved its headquarters from Dublin, Ireland to San Jose,
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Today Analog Devices announced four new members of its SHARC family. These new chips primarily target audio applications, and have a variety of audio-specific peripherals and I/O ports. The new chips include the ADSP-21266, ’21267, ’21364, and ’21365.
The ’21266 and ’21267 primarily target car audio systems. The ’21266 is currently sampling at 150 MHz, and the ’21267 will begin sampling at 200 MHz in the first quarter of 2004. The ’21364 and ’21365 target high-performance car and
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As we approach year-end, it seems fitting to look back at developments and trends in DSP processors. And it’s an opportune time to do so, since my colleagues and I just completed the latest iteration of our exhaustive (and exhausting) study of leading DSPs. It has been three years since we published the previous edition, and in reviewing the new version I am struck by one of the key changes in our industry.
Back in 2000, telecom was the DSP killer app. Most DSP architectural innovations
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Last month StarCore announced that it is offering two DSP cores for license. StarCore, originally formed in 1999 as a joint design center for Agere and Motorola, introduced the SC140 DSP core in 2000. The SC140 has since been used in chips from Motorola, but has not been available for license by other companies. Last year, StarCore made major changes to its business model (see DSP Insider, July 2002), and announced its intention to begin licensing DSP cores.
StarCore is now licensing a
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At the Microprocessor Forum last month, Renesas and SuperH debuted the latest processor in the SuperH family, the SH-X. The SH-X is a synthesizable 32-bit fixed-point CPU core that is object-code compatible with its 32-bit predecessors, which include the SH-3, SH3-DSP, and SH-4. Renesas expects to begin shipping SH-X-based chips in early 2004. It is not yet clear whether the core will be available for license; SuperH Inc., which is responsible for SuperH core licensing activities, did not
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At last month’s Microprocessor Forum, Sun Microsystems CTO Greg Papadopoulos predicted that microprocessors as we know them will disappear by 2010. In his view, microprocessors will continue to absorb surrounding chips until the entire computer is contained in a single chip. This prediction reminded me of claims by Texas Instruments that cell phones will soon contain nothing more than a single chip and a handful of passive components.
There is no denying the trend towards higher integration
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Last month Motorola introduced the MC56F83xx family of control-oriented DSPs. The MC56F83xx is the second processor family based on the 56800E core. It succeeds the DSP56F8xx, which uses the older, slightly less efficient 56800 core. All six members of the MC56F83xx family operate at an instruction cycle rate of 60 MHz, making them about 50% faster than the DSP56F8xx. (The DSP56F8xx operates at clock rates of up to 80 MHz, but requires two clock cycles per instruction.) In addition, the
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On August 11, Analog Devices (ADI) introduced a new chip in its floating-point DSP line, the ADSP-21262. The ’21262 is based on ADI’s dual-MAC SIMD core, which ADI originally dubbed “Hammerhead.” ADI now refers to the ’21262 as a “third-generation SHARC,” presumably to emphasize the chip’s assembly-code compatibility with the earlier ADSP-2106x chip family and to differentiate these two families from ADI’s high-performance TigerSHARC chips. The ’21262 is currently sampling at 200 MHz and 1.2
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