"If it has speech recognition, why do we have to use our fingers?" According to Bernie Brafman, Vice President of Business Development at Sensory, that simple question has been at the forefront of many of the company's customers' minds throughout Sensory's 19-year existence. That same question has therefore guided the privately held company's technology and product roadmap. But actualizing this aspiration involves, at first glance, difficult tradeoffs. Always-active speech recognition requires
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Soon after BDTI got its start in the early 1990s, we became known for our benchmarks. We benchmarked whatever types of processors people were using for embedded digital signal processing: first DSPs, then CPUs, and eventually MCUs, FPGAs, and GPUs, too.
One of the interesting things about benchmarking processors for embedded digital signal processing tasks is the importance of optimization. Optimization is central to digital signal processing applications. In a typical embedded DSP application
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Algorithms are the essence of digital signal processing; they are the mathematical "recipes" that transform signals in useful ways. Companies developing new algorithms, or considering purchasing or licensing algorithms, often need to assess whether an algorithm will fit within their processing budget—and thereby within their cost and power consumption targets.
But estimating an algorithm's processing load can be difficult if the algorithm has not already been carefully mapped onto the target
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Back in September 2011, an InsideDSP article described a just-published analysis conducted by BDTI and sponsored by Altera, evaluating the viability of implementing complex hardware-accelerated single-precision floating-point functions on FPGA fabric. As I wrote then:
To date, FPGAs have been used almost exclusively for fixed-point digital signal processing functions. Although FPGA vendors have long offered floating-point primitive libraries, the performance of FPGAs in floating-point
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In a recent interview in EE Times, BDTI co-founder and president Jeff Bier commented:
Multi-core CPUs are very powerful and programmable, but not very energy-efficient. So if you have a battery-powered device that is going to be doing a lot of vision processing, you may be motivated to run your vision algorithms on a more specialized processor.
Bier could have been speaking about CEVA's MM3101 processing core, which InsideDSP covered in its January 2012 edition. Or he could have been referring
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If you’re a regular reader of this column, you know that I’m enthusiastic about the potential of “embedded vision” – the widespread use of computer vision in embedded systems, mobile devices, PCs, and the cloud. Processors and sensors with sufficient performance for sophisticated computer vision are now available at price, size, and power consumption levels appropriate for many markets, including cost-sensitive consumer products and energy-sipping portable devices. This is ushering in an era
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Qualcomm recently opened up the QDSP6 (aka "Hexagon") DSP core in its Snapdragon SoCs to programming access by its customers and software developer partners. Multimedia applications, for example, can benefit from leveraging QDSP6 processing resources, boosting overall performance, minimizing overall power consumption, and freeing up the CPU to tackle other tasks. And mobile application processors such as Snapdragon are increasingly finding use in a diversity of embedded applications beyond the
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The article, "QDSP6 V4: Qualcomm Gives Customers and Developers Programming Access to its DSP Core," which appeared in the June 2012 edition of InsideDSP, showcased Qualcomm’s decision to open up access to its DSP core via a software development kit. This decision corresponded with the release of the fourth version (V4) of the sixth generation (QDSP6, aka "Hexagon") of the company's proprietary DSP architecture, found in the company's 28 nm-based Snapdragon S4 SoCs.
To be clear, this broadened
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Within a technical article published in the August 2012 edition of InsideDSP, I wrote:
As FPGAs have evolved, the means by which engineers create FPGA designs have also evolved. In particular, design techniques employing increasingly higher levels of abstraction have been required to address the increasing chip capabilities. Initial FPGA design flows were schematic-based. These later gave way to HDLs (hardware description languages) such as VHDL and Verilog. And more recently, high-level
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In my December column, I wrote about how smartphones and tablets are subsuming some categories of consumer electronics, such as MP3 players and networked home audio players. Because smartphones and tablets are network-centric devices, their growing use as media players is contributing to another important trend: multimedia content is increasingly being delivered on-demand via the Internet. These days, I get nearly all of my new audio entertainment content, such as podcasts and streaming music,
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