Software Development

ARC Introduces Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1. (The middle of the family range is filled out by the AV 404V, AV 406V, and AV 407V) are intended for compression-centric applications such as camera phones, portable media players, Read more...

How Video Compression Works

Digital video compression/decompression algorithms (codecs) are at the heart of many modern video products, from DVD players to multimedia jukeboxes to video-capable cell phones. Understanding the operation of video compression algorithms is essential for developers of the systems, processors, and tools that target video applications. In this article, we explain the operation and characteristics of video codecs and the demands codecs make on processors. We also explain how codecs differ from Read more...

Tensilica Offers High-Performance Licensable Video Engine

Tensilica is now offering a high-performance licensable video engine capable of MPEG-4 ASP encoding at D1 resolution. The processor is called the Diamond 388VDO, and it’s one of four new dual-core “VDO” video engines from Tensilica.  The 388VDO is the highest-performance member of the quartet and supports a variety of video codec standards at resolutions up to D1 (i.e., standard definition television). Target applications include chips for mobile handsets and personal media players. In its Read more...

Jeff Bier’s Impulse Response—Signal Processing Algorithms Easier to Create, Harder to Sell

  One of the things I really love about digital signal processing technology is how, year by year, it gets easier to create new things.  Things like clever new audio or video compression algorithms, for example. Forget about needing mainframes, minicomputers, or expensive engineering workstations to evaluate that new algorithm. Today we’ve got powerful PCs and easy-to-use simulation environments that make the whole process relatively painless. Forget about the time, money, and risk Read more...

Massively Parallel Processors for DSP, Part 1

In the last few years a number of start-up companies have announced massively parallel processors for embedded DSP applications.  With their arrays of processing elements, these processors target high-end digital video, software-defined radio and other computationally demanding applications for which traditional DSP processors lack sufficient horsepower and ASICs are too inflexible or too costly to design. In some cases, massively parallel architectures are employed to reduce power Read more...

MIPS Announces High-Performance Superscalar Core

MIPS has introduced the MIPS 74K, a new, high-performance synthesizable general-purpose microprocessor core. The 74K targets demanding multimedia and networking applications, such as H.264 and WiMaX, and according to MIPS, the core has already been shipped to initial licensees. The 74K is a 32-bit, dual-issue, asymmetric superscalar architecture that supports out-of-order instruction execution and uses a 17-stage pipeline. According to MIPS, the 74K can achieve speeds of up to 1 GHz when Read more...

Plurality’s Hypercore Joins the Multi-Core Fray

There’s no shortage of startup companies with massively parallel processor architectures targeting high-performance signal processing applications, but Israel-based newcomer Plurality (www.plurality.com) isn’t discouraged. The company recently introduced a new multi-core architecture, Hypercore, that can support from 16 to 256 RISC processors on a single chip. Plurality is betting that its patented “synchronizer/scheduler” hardware—which the company claims enables “the programmability of a Read more...

CEVA Unveils “Lite” Mobile Multimedia Platform

In March CEVA unveiled “Mobile-Media-Lite” (MMLite), a family of multimedia processing solutions comprising licensable silicon IP and software. The family is aimed at low-end multimedia-enabled devices such as mobile TV players, portable multimedia players, and multimedia phones. CEVA also announced the first family member, the MM2200, a single-processor multimedia engine. CEVA’s intent is to provide highly integrated, application-optimized solutions; the company states that the MM2200 is Read more...

Xilinx Spartan gets DSP

In recent years, FPGA vendors have been aggressively pursuing high-performance signal processing applications. This month Xilinx broadened its target DSP markets by announcing a new lower-cost DSP-oriented FPGA family, Spartan-3A DSP. Spartan-3A DSP FPGAs are intended to provide better DSP performance than other Spartan devices while being less expensive than Xilinx’s high-performance Virtex-4 and Virtex-5 families. The new chip family targets cost-sensitive applications with high computational Read more...

Case Study: Multi-Tiered Software Optimization

It’s generally accepted that, for processing engines, there is a trade-off between efficiency and generality.  The more a chip is geared towards a specific application, the more efficient it’s likely to be (in terms of speed, energy consumption, and cost).  On one end of the spectrum you have traditional FPGAs, which are completely general-purpose, and on the other are fixed-function chips, which are completely application specific. In between these extremes lie various types of processors, Read more...