In early 2015, Synopsys' DesignWare EV5x processor core family achieved notable attention for its unique co-processor engine focused on CNNs (convolutional neural networks) for object recognition and other vision functions. The company's new EV6x processor core family includes an upgraded CNN engine that delivers substantial performance gains over its predecessor while – in a nod to customers preferring to leverage "classical" computer vision algorithms – decoupling it from the remainder of the
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Just last October, Cadence announced the then-latest generation in its computer vision processor core roadmap, the Tensilica Vision P5. Only seven months later, the Vision P5 has been superseded by the Vision P6 (Figure 1). This rapid product development pace reflects the equally rapid expansion and evolution of embedded computer vision applications. According to Cadence’s Chief Technology Officer Chris Rowen and Director of Product Marketing Pulin Desai, the company's new vision core is the
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In late January of this year, Movidius and Google broadened their collaboration plans, which had begun with 2014's Project Tango prototype depth-sensing smartphone. As initially announced, the companies’ broader intention to "accelerate the adoption of deep learning within mobile devices" was somewhat vague. However, as of earlier this month, at least some of the details of the planned collaboration become clearer, thanks to the unveiling of Movidius' Fathom Software Framework and Neural
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CEVA's DSP cores have long been a fixture in many mobile phone cellular modems, where they handle the tranceiver's digital signal processing functions, working alongside function-specific hardware accelerators. However, the physical layer coordination between the transmit and receiver subsystems, along with overall modem control and other housekeeping tasks, has long been the bailiwick of a real-time CPU core from ARM, Imagination Technologies or another supplier. CEVA aspires to evolve this
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Hear the words "high volume DSP market" and you might automatically think of "mobile phones". And you'd be right; recent estimates peg quarterly worldwide mobile phone shipments approaching half a trillion units, with smartphones (which often contain multiple DSP cores) representing three-quarters of that amount. However, CEVA believes that in the not-too-distant future, alternative markets with similar cellular connectivity needs—wearables, connected vehicles, and a diversity of IoT devices—
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In 2013, Tensilica (subsequently acquired by Cadence) released its second-generation image processing IP core, the IVP, which also supported modest computer vision capabilities (Figure 1). One year later came the IVP-EP, which supported increased data precision flexibility, boosting overall performance in many applications and therefore further expanding the core's vision processing function reach. And in October of this year, Cadence further extended the product line, unveiling its latest
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A growing number of products are incorporating computer vision capabilities. This, in turn, has led to rapid growth in the number of processors being offered for vision applications. Selecting the best processor (whether a chip for use in a system design, or an IP core for use in an SoC) is challenging, for several reasons.
First, these processors use very diverse architecture approaches, which makes it tough to compare them. Second, because vision applications and algorithms are also quite
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As Jeff Bier has mentioned in several of his recent columns, deep learning algorithms have gained prominence in computer vision and other fields where there's a need to extract insights from ambiguous data. Convolutional neural networks (CNNs) – massively parallel algorithms made up of layers of computation nodes – have shown particularly impressive results on challenging problems that thwart traditional feature-based techniques; when attempting to identify non-uniform objects, for example, or
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Qualcomm has been evolving its in-house DSP core for many years. Originally developed for use in Qualcomm’s cellular modems, more recently it has also found use as an application co-processor, offloading multimedia tasks from the CPU in smart phones and tablets. Earlier InsideDSP articles covered the v4 "Hexagon" DSP core in mid-2012 and early 2013, along with the v5 Hexagon architecture later that same year. Now, with its Hexagon v6 DSP core, which will see its first silicon implementation in
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In May 2014, Synopsys expanded its ARC EM licensable processor core product line, which BDTI described as historically being "vanilla" Harvard architecture CPUs with no DSP-optimized features, via the addition of the digital signal processing pipeline-equipped EM5D and EM7D (“D” denoting DSP). This year's follow-on EM9D and EM11D make what at first glance seem to be minor upgrades, in the form of an optional incremental 2-64 KB of special-purpose embedded memory. But, according to company
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