On March 5, Stretch, Inc. announced its second-generation software configurable processor family, the S6000, and two initial chips. With this offering—its first since the appointment last year of a new CEO—Stretch is mainly targeting video surveillance, video broadcast, and WiMAX basestation applications.
The S6000, like the previous-generation S5000 family, is a RISC processor which incorporates a reconfigurable compute fabric within its datapath. The fabric (which Stretch calls ISEF) allows powerful custom instructions to be inserted into the processor’s instruction set at run-time via software. In addition, in the S6000 Stretch has added fixed-function hardware accelerators for motion estimation, entropy encoding, encryption, and audio encoding and decoding. Also added are interprocessor communication links; Stretch maintains that this will lower the cost of solutions employing multiple S6000 devices. (Connecting multiple S5000 chips, in contrast, required the use of FPGAs.) The S6000 devices are also significantly less expensive ($34-39, versus $70-85 for the S5000 devices.) (All prices in this article are for 10,000-unit purchases.)
The ISEF, used for accelerating compute-intensive application code that does not map onto the fixed-function accelerators, has also been enhanced. In the S6000 devices, the ISEF runs at 300 MHz (versus 100 MHz in the S5000) and features an extended register set, 64 KB of embedded RAM (the S5000 had none), and architectural enhancements that allow the ISEF to be reconfigured four times faster than the S5000 ISEF.
The starting point for programming the S6000 is a C/C++ application program. Using Stretch’s integrated development environment, the programmer flags compute-intensive sections of the code, which the compiler transforms into custom instructions for the ISEF. Tens or hundreds of operations can be collapsed into a single custom instruction, according to Stretch. Fixed-function accelerators are invoked in the C/C++ code via function calls.
The combination of fixed-function accelerators and the ability of the ISEF to accelerate many different algorithms may give the S6000 a throughput advantage over high-end DSPs in the targeted applications. Stretch reports that the S6000 devices can perform four channels of H.264 Baseline Profile video encoding at D1 resolution, which Stretch claims is four times the throughput of TI’s video-oriented DaVinci DM6446. (The DM6446 is similarly priced at $35.) It must be noted, however, that comparing processor performance using video encoders is very difficult due to variations in video quality, testing conditions, and performance metric definitions.
The S6000 devices will also compete against numerous multi-core DSPs and a range of heterogeneous solutions employing combinations of FPGAs, DSPs, CPUs, and fixed-function accelerators. Although the S6000 devices may not match the high throughput levels of these competitors, they may offer reduced development effort. Because the S6000 is a single-core architecture, application development may be significantly simpler than with multi-core devices. And because the S6000 programmer works primarily in C/C++, programming the S6000 may be easier than designing with FPGAs, which require hardware design expertise, or with conventional processors, which typically require assembly coding of critical inner loops for maximum performance.
FPGA vendors also offer processor-within-reconfigurable-hardware solutions (in contrast to Stretch’s reconfigurable-hardware-within-a-processor approach), that aim to reduce development effort. For example, Altera offers a similar programming model with its Nios II soft processor core and C2H tool: programmers profile C/C++ code and use C2H to turn compute-intensive sections into custom instructions implemented in the surrounding FPGA fabric.
According to Stretch, the announced devices, S6105 and S6100, will begin sampling later this year, with full production expected in the fourth quarter. In addition to its software development tools, Stretch offers a library of commonly used video and wireless communications building-block functions, as well as H.264 and MJPEG encoders and decoders.
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