On May 15, Xilinx, Inc. unveiled its new Virtex-5 line of field programmable gate arrays (FPGAs). The product line will consist of four distinct families, each targeting a specific class of applications. While all four families share the same basic architecture, each will have a different mixture of hard-wired blocks and I/O features geared for its targeted applications. The three currently sampling devices are from the LX family and target high-speed logic applications. The remaining three families are slated to become available in sample quantities during the second half of 2006 and the first half of 2007, and will target embedded processing, digital signal processing, and serial-connectivity-intensive applications. Significant changes from the Virtex-4 family include migration from a 90 nm process to a 65 nm triple-oxide process, improvements to the logic cell interconnect architecture, and enhancements to hard-wired blocks.
A feature of particular interest to FPGA users targeting DSP applications is the DSP48E hard-wired data path block, an enhanced version of the DSP48 block used in the Virtex-4 line. DSP48E blocks can be used to efficiently implement common DSP functions such as filters and FFTs. Enhancements in the DSP48E include an increase in multiplier precision from 18x18 to 25x18, an ALU that can perform bit-wise logical operations as well as arithmetic, and the capability to cascade inputs between DSP48E blocks. Additionally, an expanded second stage has been added that allows for up to 48-bit pattern detection on the output of the DSP48E. This could be particularly useful in some digital communications applications. Interestingly, the enhanced data path now closely resembles that of a traditional digital signal processor in many respects. The increase in multiplier precision, as well as other DSP48E enhancements, reflect the Virtex-5’s focus on high-performance DSP applications. For instance, in applications using high-precision filters, some multiplications that required two DSP48 blocks in a Virtex-4 chip can now be implemented with a single DSP48E. Applications that Xilinx believes will benefit from the DSP48E include medical imaging, baseband processing for emerging communications standards such as 3G and 4G cellular, and defense applications such as beamforming and radar.
Using 65 nm processes from Toshiba and UMC, Xilinx says that the DSP48E blocks run at 550 MHz, a 10% increase over the clock speed of the DSP48 in Virtex-4. While the clock speed increase is modest, the move to 65 nm enables Xilinx to pack more hardwired blocks into an FPGA. The LX family, for instance, includes devices that contain up to 192 DSP48E blocks. In the Virtex-4 line, only the signal-processing-oriented SX family included devices with up to 192 DSP48E blocks. Xilinx reports an increase in overall capacity of 65% relative to the Virtex-4. There have also been significant changes in the reconfigurable fabric. Most notably, these include moving to a six-input logic block and a diagonally symmetrical interconnect fabric. Together, Xilinx says that these enhancements reduce the levels of logic and interconnect required to implement a given function, boosting speed by 30% on average over Virtex-4. Xilinx also reports a 35% reduction in dynamic power relative to the Virtex-4 family with no change in static power.
The LX50, LX85, and LX110 devices are currently sampling and priced at $149, $279, and $399 respectively (prices at 1,000 unit volumes). All LX devices are expected to be in production by mid-2007. Samples of devices from the LXT and SXT families, which focus on serial connectivity and DSP applications, respectively, are expected in the second half of 2006. Samples of the FXT family, which focuses on embedded applications, are slated for release in the first half of 2007.
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