Programmable logic IP cores, intended for integration within a broader-function ASIC, are a long-discussed and –explored product option that has yet to achieve more than niche adoption. Small FPGA IP players such as Flex Logic Technologies and Menta linger in the market, but picking such a supplier for your next SoC can be a gamble; what happens if they get acquired or otherwise disappear? And big FPGA vendors like Altera (now Intel's Programmable Solutions Group) and Xilinx, along with medium-sized suppliers such as Actel (now part of Microsemi) and Lattice Semiconductor, are focused on selling standalone programmable logic ICs, with little to-date motivation to detract from those lucrative product offerings via IP licensing deals.
Achronix Semiconductor aspires to succeed where its programmable logic IP core competitors have struggled via the company's new Speedcore eFPGA technology, a complement to the company's Speedster22i FPGA chip line. Achronix gained significant visibility in 2010 when it announced a partnership with Intel to become the latter company's first 22 nm foundry customer (on which, as the name implies, Speedster22i is fabricated). However, according to Steve Mensor, the company's Vice President of Marketing, Achronix's lineage dates all the way back to 2004, when the company was founded, leveraging Cornell University research. Achronix' initial focus on asynchronous logic was thwarted by the dominant presence of loop-back functions in programmable logic-based circuit designs, which negate asynchronous logic's inherent performance advantage in feed-forward function arrangements. The company's initial PicoPipe products were also developed without emphasis on low power operation, which rendered them largely non-commercializable.
At that point, the company refocused its attention on more conventional FPGA architectures. Speedster22i devices began shipping in early 2013, followed by an FPGA-based accelerator board for data center applications earlier this year. And as Mensor explained in a recent briefing, the seeds for the new Speedcore IP line were sown earlier this decade, when Speedster22i devices were still in design (Figure 1). While the chips' programmable logic arrays were internally designed in Santa Clara, CA, the devices' I/O buffers and other peripheral circuits were sourced elsewhere and combined with the FPGA arrays by a contract design team in Bangalore, India. In effect, this integration group provided a proof-of-concept test for the sorts of licensing arrangements with SoC developers that Achronix is now pursuing with Speedcore.
Figure 1. Achronix acted as a test case for its future IP licensing aspirations when it augmented an internally-developed FPGA core (top) with third-party licensed function blocks (middle) together comprising the Speedster22i FPGAs' peripheral ring (bottom), and all merged together by an overseas contract design team.
While the Speedster22i FPGA array provides the foundation for Speedcore, the company has incorporated process and design enhancements during the new IP core's development. For one thing, while Speedcore supports both Intel's 22 nm and newer 14 nm processes, it's also qualified on TSMC's 16 nm FF+ (FinFET) process, which the company believes most near-term customer implementations will use. Achronix also made the architecture more modular with respect to its multi-LUT (lookup table) logic block, BRAM (block RAM) and LRAM (logic RAM) structures, as well as the interconnects between them, thereby easing the ability to tailor their respective locations and allocations for any particular customer implementation (Figure 2).
Figure 2. Speedcore function blocks improve modularity (top) for enhanced customizability (bottom).
Of particular interest to InsideDSP readers, the company has also significantly enhanced what were previously simple "big multipliers" on Speedster22i, transforming them into fuller-featured DSP acceleration blocks natively supporting numerous functions (Figure 3):
- 18- x 27-bit multiply
- 18- x 27-bit multiply with 64-bit accumulate and optional rounding
- 18-bit (add or subtract)2
- 27-bit (add or subtract) x 18-bit constant (dynamic selection of 1 of 8 from register file)
- 1⁄4 of a 18- x 27-bit complex multiply
- Systolic FIR filters (27-bit data, 18-bit coefficients)
- Even/odd length, symmetric/anti-symmetric impulse response
- Multiple rounding modes
- Saturation detection circuitry
- 18- x 27-bit multiply + 48-bit third input (requires two DSP blocks)
- Cascadable 48-bit add/subtract (requires two DSP blocks)
Figure 3. Highly integrated DSP blocks deliver improvements in performance, power consumption and silicon area utilization versus precursor elementary multipliers.
Mensor acknowledged that with the prior multiplier-only approach, a significant amount of additional pipelining and other circuitry constructed from generic programmable logic structures would often need to be added in order to construct a meaningful DSP function, which hampered overall performance along with other key metrics. By integrating this additional logic within the newly enhanced DSP block, speed, aggregate power consumption and required silicon area are all improved in Speedcore. And while Achronix is not yet ready to delve into detail on its next-generation FPGA chip product line, it's a good bet that the enhanced DSP block will be included there, as well.
Achronix's business model for Speedcore involves an unspecified initial license fee for access to the technology, along with royalties on shipments of devices that integrate Speedcore, and design tool maintenance charges (Achronix licenses Synopsys' Synplify-Pro synthesis toolset). Deliverables include GDSII or OASIS "hard" core integration files, simulation files, signal and power integrity models, test and timing characterization data, and documentation. To interface the Speedcore IP to the rest of your SoC, you'll need to rely on Achronix' proprietary I/O scheme, at least for now (Figure 4). While Mensor touts the I/O buffers' high performance (a maximum toggle rate of 500 MHz, along with 2 ns maximum latency), he also acknowledges that the proprietary approach can hamper ease of integration versus an ARM AMBA or other standardized bus, and suggests that the company is looking at alternative interface schemes for the future.
Figure 4. Achronix's current proprietary I/O interface scheme may be highly efficient, but more industry standard, easily integrated alternative approaches are also under consideration for future offerings.
In closing, Mensor emphasized that the Speedcore IP product line represents an expansion of the company's focus beyond discrete programmable logic chips, not a redirection away from them. To wit, after Intel's recent acquisition of Altera, and despite Intel’s more recent executive pronouncements and product announcements, Mensor claims that legacy Altera customers still fear that sooner or later, they'll be left without ongoing FPGA supply from the company. Couple this with seemingly uncertain ongoing programmable logic market commitments from Lattice (which last year expanded its market and product focus via the acquisition of Silicon Image, and more recently has been taken private), Microchip and Microsemi, and Mensor sees ripe opportunity for his company to step in and provide a true alternative IC source to "last FPGA device vendor standing" Xilinx, in parallel with cultivating its embryonic IP business.
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