Altera Jumps to 40 nm with Stratix IV

Not to be outdone by rival Xilinx, Altera has made a major announcement of its own. In mid-May, Altera unveiled its next-generation high-performance FPGA family, the Stratix IV, and announced that the family will be fabbed in a 40 nm TSMC process.  Xilinx beat Altera to the 65 nm node with its Virtex-5 chips, but with this announcement, it appears that Altera will leapfrog Xilinx to 40 nm—assuming that Xilinx doesn’t come out with 40 nm chips before the Stratix IV is expected to start sampling, towards the end of this year.

The new Stratix IV chip family will include 12 members:  six GX devices, and six E devices.  GX chips have from 8-48 high-speed serial transceivers, while the E devices have no transceivers but more memory and more DSP-oriented features.  The highest capacity Stratix IV chips will have roughly double the logic capacity of the biggest Stratix III chips—up to 680K logic elements. The new chips will also include up to 22.4 Mbits of internal RAM. Pricing has not yet been announced.

Figure 1. Stratix IV chips. (Data courtesy of Altera)

Stratix IV chips will include hardwired DSP blocks that are somewhat analogous to Xilinx’s DSP slices.  However, Altera’s DSP blocks are coarser grained than Xilinx’s DSP slices; each Stratix IV DSP block includes four 18x18-bit multipliers along with other hardware to support multiplication and filtering operations, and runs at up to 600 MHz, according to Altera.  The biggest Stratix IV chip will have 340 DSP blocks (1360 18-bit multipliers), compared to 192 DSP blocks on the biggest Stratix III chips.

Unlike Xilinx, Altera doesn’t offer an embedded hard processor core like the PowerPC, but it does offer a soft core, Nios II, that can be implemented in the FPGA fabric.  Soft processor cores (such as Nios II and MicroBlaze) are less efficient and operate at lower clock rates than hard cores, but offer more flexibility—the hardware can be optimized for performance and the instruction sets can be configured for specific applications.

Altera will also offer 40 nm “HardCopy” versions of the Stratix IV chips, with initial tapeouts expected in the third quarter of next year. HardCopy is a service that enables FPGA users to migrate stable Stratix designs to an equivalent fixed-function ASIC, with associated reductions in chip size, power consumption, and cost. HardCopy chips include the same high-speed transceivers as Stratix IV chips. The biggest HardCopy chip offers over 13 million logic gates.

With its 40 nm, transceiver-equipped Stratix IV, Altera is emphasizing FPGAs’ system integration capabilities and scalability, which are key advantages relative to instruction-set processors.  (Though not yet at 40 nm, Xilinx has pushed a similar message with its new high-capacity chips, particularly those with on-board transceivers and PowerPCs.) Because FPGAs use silicon in a relatively homogeneous way (unlike processors) it is easier for FPGA vendors to take advantage of increased circuit density to deliver more logic resources for the user. This can translate into higher application performance and potentially lower system costs via better system integration. As process nodes shrink, FPGA vendors may well get more “bang for the buck” out of each process migration than processor vendors. The challenge for FPGA vendors, of course, is to simplify their application development process as aggressively as they are increasing their chip capacity.