Xilinx recently introduced two new FPGA chip families, Spartan-6 and Virtex-6 that offer increased capacity and lower power consumption relative to their predecessors. For the first time, the new Spartan and Virtex families use the same underlying architecture to enable easier migration. There are, however, differences in fabrication process and features. Spartan-6 chips will be fabbed in a 45 nm process, while Virtex-6 chips will be fabbed in 40 nm. Spartan-6 chips incorporate DDR3 integrated memory controllers and support for 3.3-volt I/O; Virtex-6 chips include specialized FIFO logic, tri-mode EMAC, and System Monitor. (The System Monitor is a debug and thermal management tool that was introduced in Virtex-5.)
According to Xilinx, initial Spartan-6 chips are sampling now, with other chips in both families expected in the third quarter of this year. Specific chip pricing has not yet been disclosed, but Xilinx says it will be in the range of $2-$35 for Spartan-6 and $57-$2100 for Virtex-6. This pricing is for large quantities in the second half of 2011, which is when the chips are expected to go into volume production.
According to Xilinx, users can expect, on average, a 50% power reduction with Virtex-6 and 60% with Spartan-6 compared to previous-generation parts. Part of the power reduction with Virtex-6 will come from its support for voltage scaling options; Spartan-6 does not support voltage scaling.
Like with previous Virtex and Spartan families, Xilinx offers multiple sub-families (“platforms”) that target specific classes of applications. Virtex-6 platforms include the LXT, which offers the most logic cells; SXT, which offers higher levels of DSP performance and serial connectivity; and HXT, which is optimized for communications applications that require high-speed serial connectivity. Chip capacity is up to 760K logic cells.
Unlike Virtex-5, all of the Virtex-6 platforms include high-speed transceivers—Xilinx says that the majority of its customers require them. None of the Virtex-6 chips include the embedded PowerPC processor that is available in some Virtex-5 chips; Xilinx expects that embedded designers who need the PowerPC will stick with Virtex-5.
Spartan-6 platforms are the LX, which is the low-cost platform, and LXT, which adds high-speed transceivers. Chip capacity ranges from 4K to 150K logic cells.
All Virtex-6 and Spartan-6 family members include DSP slices. On Virtex-6, the number of slices ranges from 288 to 2016; on Spartan-6 it ranges from 4 to 182.
Xilinx plans to use the new Spartan-6 and Virtex-6 family members as the basis for both domain-specific development kits (for domains such as DSP and embedded processing, for example) and market-specific platforms. The market-specific platforms will include chips, reference designs, and IP cores (i.e., implementations of key application-specific processing tasks, like video codecs) for markets such as automotive, consumer, video, and communications. By offering more than just chips and basic design tools, Xilinx hopes to enable faster and easier application development for its customers. It’s a good strategy, and is one of several possible approaches to achieving this goal; others include offering better, more user-friendly tools, and creating processor-centric design paradigms (neither of which are mutually exclusive with Xilinx’s platform approach).
Xilinx’s new FPGA families and platforms represent not just more capacity and higher performance, but a shift towards a more application-oriented development paradigm.
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