Multithreaded programming isn't a new idea, but it's currently experiencing a major upswing in attention. That's because many multi-core chip vendors are currently pushing multithreading as the best way to harness their chips' processing horsepower.
But a recent influential paper by Dr. Edward Lee argues that multi-threaded application programming, as commonly practiced, is a flawed methodology that invites a range of nasty, hard-to-identify bugs.
Dr. Lee is a professor of EECS at UC
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Here at BDTI, we just wrapped up a new study comparing DSP-oriented FPGAs to DSP processors. Like many DSP engineers, I started the project extremely familiar with processors and relatively new to FPGAs. I've ended it with a deeper understanding of the many surprising differences between the two technologies. I'm not talking about performance differences—though our benchmark results do show some big ones. No, what I'm talking about is how data that's straightforward to obtain for processors
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Recently a friend of mine was lamenting the fact that so many new processors continue to be designed, and so few achieve any commercial success. “Why do people persist in designing new processors?” he asked. “Maybe because universities keep training processor designers,” I speculated. On closer reflection, though, I believe there’s more to the story.
Historically, processor designers created highly specialized DSP-oriented architectures with the goal of achieving real-time signal processing
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Many DSP-oriented systems are composed of multiple application tasks—e.g., an audio codec, a video codec, and a networking stack. During initial product development, the system designer typically divvies up the available processor MIPS among the tasks, and assigns the tasks to various engineering teams. These teams then go off to craft their code to stay within the MIPS they've been allocated. When all of the components are finished, the tasks are integrated together and the system designer
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I have two ways of looking at processors. If I’m in geeky-engineer mode, I’m thrilled to learn about the hard-core technical details—like how the branch prediction works, and why the DMA engine is breathtaking in its sophistication and complexity, and how the chip uses a revolutionary new method for implementing… whatever.
But if I’m in product-development mode and I have to choose a processor, the last thing I want to hear is how complicated it is. No, I want to hear how straightforward
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Say you’re looking for an H.264 video decoder solution to integrate into your system, and you’re trying to compare what's available. You figure this should be a straightforward process–after all, H.264 is a standards-based codec, so it should be easy to find apples-to-apples performance data.
You confidently search the Internet and are rewarded with a bunch of performance data. But (as is true with any multimedia solution) the format and type of data is all over the map. For example
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When does 1 GHz + 1 GHz + 1 GHz + 1 GHz not necessarily equal 4 GHz? When you’re calculating the performance potential of a multi-core chip.
Freescale recently introduced a new DSP chip, the MSC8144, that contains four 1 GHz SC3400 processor cores. Freescale characterizes the new chip as being “performance-equivalent” to one 4 GHz core. But is it really? As usual, the answer is, “It depends.” It depends on what kind of application you’re running, how you map the application onto the
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The next time you’re choosing an embedded processor, you should consider choosing an FPGA. This was the take-home message from FPGA vendors at the Embedded Systems Conference Silicon Valley in April—and in my opinion, it’s a message with merit.
Although FPGAs aren’t widely used as embedded processors today, there are some compelling advantages to doing so. In the embedded world, processor selection is often made on the basis of which chip offers the best combination of on-chip peripherals
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Every so often I get a call from someone who wants to know the gate count (or equivalently, the silicon area) of some embedded processor core. And every time this happens, I have to stifle the urge to say “Why on earth do you care?”
The reason the question baffles me is that, in chips that use embedded processor cores, the area used by the core is almost always negligible compared to the area eaten up by memory banks. It’s common for the processor core to consume only about 10% of the die
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I’m starting to wonder if executives at FPGA companies are having conversations like those of the cartoon characters in “Pinky and the Brain”:
Pinky: “Gee, Brain, what are we going to do today?”
Brain: “The same thing we do every day, Pinky—try to take over the world!”
Clearly FPGA vendors are no longer content to provide a little glue logic here and there. A few years ago they started pushing hard into the multi-billion-dollar DSP space, and now (as I wrote in the April 2006 Impulse
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