Freescale has announced a new high-performance DSP product line, the MSC825x, incorporating up to six StarCore SC3850 DSP cores at up to 1 GHz. Unlike other high-performance DSPs introduced by Freescale in recent years—which were aimed almost exclusively at wireless infrastructure applications—the new chips target a range of performance-intensive applications, including medical, aerospace and defense, and test and measurement equipment. This will put the new chips in direct competition with
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BDTI recently completed an in-depth evaluation of Synfora’s PICO tool through the BDTI High-Level Synthesis Tool Certification Program™. BDTI evaluated the process of implementing applications on a Xilinx FPGA using PICO, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development. PICO enabled creation of efficient FPGA implementations, with design productivity comparable to that of DSP processor software development. The
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BDTI recently completed an in-depth analysis of AutoESL’s AutoPilot high-level synthesis tool via the BDTI High-Level Synthesis Tool Certification Program™. BDTI evaluated the process of implementing applications on a Xilinx FPGA using AutoPilot, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development. Overall, AutoPilot demonstrated a strong ability to generate high-quality RTL code—with equivalent resource utilization to hand-
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This week BDTI released the first results from its High-Level Synthesis Tools Certification Program (HLSTCP). The first tools to achieve certification are AutoESL’s AutoPilot and Synfora’s PICO. Additional certifications will be released on an ongoing basis, as agreements with tool vendors allow. The HLSTCP helps engineers and managers understand the capabilities of high-level synthesis (HLS) tools and assess when to consider these tools for their designs. HLS tool vendors can use the
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Processor designers know that a cycle-accurate simulator can be used to benchmark a processor that has not yet been fabricated. But many designers don’t realize that it’s also possible to benchmark an idea for a processor, a processor that may exist only in PowerPoint slides—and that there are good reasons for doing so.
As BDTI’s president Jeff Bier wrote in a recent column, BDTI has seen a number of cases in which a processor vendor used BDTI’s benchmarks on its fully-designed processor,
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BDTI recently completed a benchmark analysis of the Toshiba MeP “Media embedded Processor” core and “IVC2” SIMD coprocessor, both of which are used in Toshiba’s Venezia mobile multimedia platform.
The MeP is a licensable core that is intended to be used as a building block in multi-core, multimedia-oriented SoCs, typically with multiple MeP cores on a chip. Each MeP core can be customized with specialized instructions, co-processors, and memory sizes.
The base MeP core is a single-issue
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BDTI has released BDTI DSP Kernel Benchmarks™ results for the CEVA-TeakLite-III core from CEVA. As we’ve written previously, CEVA-TeakLite-III is a 32-bit DSP core that primarily targets audio applications (both portable and high-definition) but also targets VoIP and cellular baseband. It is the third generation of CEVA’s TeakLite architecture, and the first to use a native 32-bit data size. The CEVA-TeakLite-III also supports SIMD (single-instruction, multiple data) dual-16-bit MACs.
The
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BDTI has released BDTI DSP Kernel Benchmarks™ results for the SideWorks signal processing engine from CoreWorks, a Portugal-based vendor of licensable silicon intellectual property. SideWorks is a licensable DSP accelerator targeting cost and power-sensitive applications such as multimedia and communications. The core is both configurable (i.e., hardware resources included in a specific implementation are selected prior to fabrication) and reconfigurable (i.e., the movement of data and some
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BDTI has released the first independent benchmark results comparing the performance of the Sandbridge “Sandblaster” SB3500 multi-core DSP chip to that of massively parallel chips, high-performance DSP processors, and FPGAs.
Sandbridge Technologies, Inc. is a fabless semiconductor company that sells multi-core chips targeting mobile 3G and 4G baseband and multimedia processing. The SB3500 chip includes three DSP cores along with an ARM core; each of the DSP cores supports four-way
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Processor and SoC vendors are always looking for the next “killer app.” To enter a new market, though, vendors face two key challenges. First, they must ensure that their product is competitive; and second, they must convince prospective customers of their product’s advantages. These challenges are tough to overcome in new markets due to a lack of well-understood application requirements and established benchmarks. In addition, it is often difficult to obtain reliable information about
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