In December Texas Instruments announced the TCI6487 multi-core baseband processor. The device will be manufactured in a 65 nm process and is intended mainly for GSM, TD-SCDMA and WiMAX basestation applications.
The TCI6487 features three TMS320C64x+ DSP cores running at 1 GHz. In comparison, its predecessor, the TCI6482, featured a single 1 GHz ‘64x+ core. TI has also added an antenna interface supporting OBSAI and CPRI protocols.
DSP cores in the TCI6487 communicate with each other and
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Editor’s Note: The past year or so has brought a wave of parallel-processor start-ups pursuing digital signal processing applications. But what about the previous wave? In the late 1990s and into 2001, a large number of start-ups emerged with unique processor architectures targeting applications like wireless infrastructure. The vast majority of these, such as Chameleon, Morphics, and Quicksilver, are long gone. PicoChip, founded in 2000, is an interesting exception. In this article,
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In November Altera announced the Stratix III family, its next generation of field-programmable gate arrays (FPGAs). The new devices will be fabricated in a 65 nm process and feature a number of significant architectural changes. To reduce power consumption, Altera has introduced “Programmable Power Technology,” which allows blocks of logic that don’t need to run at maximum speed to run in a slower, low-power mode. The sizes of hard-wired memory blocks have been changed relative to the
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Here at BDTI, we just wrapped up a new study comparing DSP-oriented FPGAs to DSP processors. Like many DSP engineers, I started the project extremely familiar with processors and relatively new to FPGAs. I've ended it with a deeper understanding of the many surprising differences between the two technologies. I'm not talking about performance differences—though our benchmark results do show some big ones. No, what I'm talking about is how data that's straightforward to obtain for processors
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Many high-performance DSP and general-purpose processors are equipped with SIMD single-instruction, multiple data) hardware and instructions. SIMD enables processors to execute a single instruction (say, an addition) on multiple independent sets of data in parallel, producing multiple independent results.
SIMD support has become increasingly common because it improves performance on many types of DSP-oriented applications (which tend to perform the same operations over and over again). But
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This week, Analog Devices introduced four new members of its Blackfin processor family: the ADSP-BF549, ‘BF548, ‘BF544, and ‘BF542. These new devices will operate at clock speeds of up to 600 MHz and are intended mainly for automotive applications that incorporate signal processing, such as digital broadcast radio receivers, navigation systems, and rear-seat entertainment equipment.
The new devices feature more on-chip memory than most Blackfin devices (only the high-performance ‘BF535
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Texas Instruments, Inc. (TI) this week announced four new “DaVinci”-branded processors: the TMS320DM6437, TMS320DM6435, TMS320DM6433 and TMS320DM6431. Priced at $10-23, the media processors target video applications in the car and the home. (All prices in this article are for 10,000 unit quantities.)
The new devices are architecturally similar to the first DaVinci chips, the ‘DM6446 and ‘DM6443. These chips and the new ‘DM643x devices both feature a ‘C64x+ core and varying assortments of
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Comparing licensable processor cores and quantifying their relative performance is challenging. Unlike processor chips, there are many different ways in which licensable cores can be configured, implemented, and fabricated, each of which yields a different combination of speed, area, and power consumption. Particularly for digital signal processing applications (which tend to push the limits on one or more of these metrics) it’s essential to have reliable and accurate performance data.
To
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BDTI has released independent benchmark results for the ARM1176 licensable processor core on the BDTI DSP Kernel Benchmarks™, which measure overall signal-processing performance, and the BDTI Video Decoder Benchmark™, which measures performance on video decoding and similar workloads.
Based on its results on the BDTI DSP Kernel Benchmarks™, the ARM1176 achieves a BDTImark2000™ score of 1200 at a clock rate of 335 MHz (All processor core performance data in this article assumes use of the
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Many DSP-oriented systems are composed of multiple application tasks—e.g., an audio codec, a video codec, and a networking stack. During initial product development, the system designer typically divvies up the available processor MIPS among the tasks, and assigns the tasks to various engineering teams. These teams then go off to craft their code to stay within the MIPS they've been allocated. When all of the components are finished, the tasks are integrated together and the system designer
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