CEVA Rolls Out New Programmable Multimedia IP Core for HD Video

Submitted by BDTI on Wed, 04/21/2010 - 19:00

CEVA recently announced its third-generation video processor IP offering.  The CEVA-MM3000™ is a programmable subsystem which is designed to support video decode and encode using many video standards, including H.264, VC1, RealVideo and AVS at resolutions up to 1080p (1920×1080 resolution at 30 or 60 frames per second). The CEVA-MM3000 is designed for use in several classes of digital media products including smartphones, tablets, Blu-ray DVD players and set-top boxes.

Analog Devices Introduces Lower-Cost SHARC Processors

Submitted by BDTI on Wed, 04/21/2010 - 19:00

Analog Devices, Inc (ADI) has announced new members of its floating-point SHARC processor family featuring lower prices and offering LQFP packages, which are easier to use in older, lower-cost manufacturing facilities. The new SHARC products target digital audio, industrial, automotive, and medical markets.  New ADSP-2147x chips feature lower power than previous SHARC products, while ADSP-2148x parts feature high performance with greater integration.

AutoESL’s AutoPilot High-Level Synthesis Tool Achieves BDTI Certification

Submitted by BDTI on Tue, 02/16/2010 - 21:00

BDTI recently completed an in-depth analysis of AutoESL’s AutoPilot high-level synthesis tool via the BDTI High-Level Synthesis Tool Certification Program™. BDTI evaluated the process of implementing applications on a Xilinx FPGA using AutoPilot, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development. Overall, AutoPilot demonstrated a strong ability to generate high-quality RTL code—with equivalent resource utilization to hand-written RTL code.

Texas Instruments Introduces New Multi-Core System-On-Chip Architecture

Submitted by BDTI on Tue, 02/16/2010 - 16:00

TI has unveiled a new chip-level architecture for high-performance, multi-core DSP-processor-based SoCs.  Most notable among its features are new on-chip and chip-to-chip interconnection mechanisms, an upgraded high-performance DSP core, and both hardware and tools support for programming concurrent applications.  The architecture is optimized to run at 1.0 to 1.2 GHz in 40 nm process technology.