Processors

Jeff Bier’s Impulse Response—Picking a Winning Processor

Last month BDTI completed an analysis of the latest DSP cores from the three leading core licensors. Paging through the analysis, I noticed some striking similarities between these competing cores. All three cores use flexible, multi-issue architectures. All three use RISC-like instruction sets. And all three use a mix of 16- and 32-bit instructions. Interestingly, these basic architectural features are also found in many high-end embedded general-purpose processors (GPP). And the Read more...

Altera Unveils Unique Structured ASICs

On Monday Altera announced HardCopy II, the latest in its line of structured ASIC offerings. Like Altera’s previous structured ASICs, HardCopy II allows designers to migrate an FPGA design to a more efficient device once programmability is no longer needed. Just as the original HardCopy could only be used with Altera’s Stratix FPGAs, HardCopy II can only be used with Stratix II FPGAs. HardCopy II chips cost roughly one-tenth as much as equivalent Stratix II FPGAs. And, according to Altera Read more...

CEVA Boosts TeakLite Speed

This month CEVA introduced the CEVA-TeakLite-II, a derivative of its widely licensed CEVA-TeakLite DSP core. The CEVA-TeakLite-II differs from its predecessor mainly in terms of speed. According to CEVA, a CEVA-TeakLite-II achieves a worst-case clock speed of 200 MHz, making it roughly 30% faster than the CEVA-TeakLite. (All performance and area figures in this article are for the TSMC CL013G process.) Interestingly, CEVA was able to achieve this increase in clock rate without increasing the Read more...

Jeff Bier’s Impulse Response—Thinning the Ranks

I recently had occasion to pick up a copy of the first edition of BDTI’s Buyer’s Guide to DSP Processors, which was published 11 years ago. Flipping through the pages reminded me of how far DSP processors have come since 1994, when 3.0 volts was “low-voltage,” 50 MHz was “impressive speed,” and a 20 MHz Analog Devices ADSP-2115 sold for $21. One thing that struck me was that eleven years ago there were actually more vendors offering general-purpose DSPs (as opposed to application-specific Read more...

ZSP Family Adds Low-End, High-End Cores

LSI Logic recently added two new processors, the ZSP200 and the ZSP540, to its ZSP family of superscalar DSP cores. With the addition of these cores, the ZSP family has become the largest family of code-compatible DSP cores available today. As with existing family members—the ZSP400, ZSP500, and ZSP600—the names of the new cores reflect their levels of parallelism. The ZSP200 offers less parallelism than the ZSP400, while the ZSP540 falls between the ZSP500 and ZSP600 in terms of parallelism Read more...

Analog Devices Announces Speedy New SHARCs

Yesterday Analog Devices announced the latest members of its SHARC family of floating-point DSPs, the ADSP-21367 and ADSP-21368. The '21367 targets high-end consumer audio applications such as home theater systems, and the '21368 targets professional audio applications such as mixing consoles. The '21367 and '21368 are identical in most respects. Both will operate at 400 MHz; both will include 256 Kbytes of RAM and 768 Kbytes of ROM; and both will offer a variety of audio-specific peripherals Read more...

Freescale, LSI, and TI Announce Thrifty, Tiny DSPs

Three small, low-cost DSPs were announced in the last few weeks: the Freescale DSP56324, the Texas Instruments TMS320C5405, and the LSI Logic LSI403LC. All three parts are relatively inexpensive, but the LSI403LC is particularly cost-effective. The 120 MHz LSI403LC is priced at $3.96, compared to $4.53 for the 150 MHz DSP56324 and $5.20 for the 80 MHz 'C5405 (all prices are for 10,000-unit quantities). A comparison of BDTImark2000 scores shows that the LSI403LC offers about 40% more speed per Read more...

Jeff Bier’s Impulse Response—DSP: The Flavor of the Week?

Last month MIPS announced a set of signal-processing-oriented instruction set extensions for its RISC architecture. Although these extensions significantly improve the signal-processing capabilities of the MIPS architecture, they won't win MIPS any special attention—all the other major general-purpose processor architectures have been offering signal-processing-oriented features for years. Indeed, it is starting to become difficult to find a processor that doesn't include some kind of signal Read more...

Jeff Bier’s Impulse Response—Processor Vendors’ Tool Dilemma

Signal processing applications are becoming more complicated, and so are the processors that run them. As a result, application developers rely on compilers and other tools more heavily than ever. This has made tools a decisive factor in processor-selection decisions. Indeed, differences in tools are a central consideration when choosing between a digital signal processor (DSP) and a general-purpose processor (GPP). DSP vendors often take a go-it-alone approach when it comes to tools: In Read more...

ARM, MIPS add DSP Extensions

This month both ARM and MIPS announced new signal-processing-oriented instruction set extensions for their future processor lineups. ARM’s extensions, which it calls NEON, will greatly expand the signal processing capabilities of the ARM architecture. NEON will add a register file organized as 32 64-bit registers or 16 128-bit registers. NEON will operate on these registers using single-instruction multiple-data (SIMD) operations that treat each register as packed 8-, 16-, 32-, or 64-bit data Read more...