BDTI Releases C55x+ Benchmark Results

Submitted by BDTI on Tue, 04/25/2006 - 17:00

Today BDTI released the first independent benchmark results for the Texas Instruments C55x+ processor core. As its name implies, the C55x+ is based on the C55x architecture. Unlike the C55x, which is available in a variety of chips, the C55x+ will be available only in custom chips for wireless handsets. The first of these products is expected to sample in the first quarter of 2007, with full production expected in 1Q08.

BDTI found that the C55x+ will achieve a BDTIsimMark2000™ score of 3160 at 500 MHz. The C55x cores used in TI’s current wireless handset products operate at a top speed of 250 MHz. At this speed, the C55x achieves a BDTImark2000™ score of 1210. Thus the C55x+ will be roughly 2.5 times faster than today’s C55x wireless handset processors. (The BDTImark2000™ and BDTIsimMark2000™ provide summary measures of signal processing speed. For more info and scores see www.BDTI.com/Resources/BenchmarkResults/BDTImark2000.)

Several factors contribute to this leap in performance. The most obvious factor is the increase in clock speed. The increased clock speed is made possible partly by moving to a smaller fabrication process: Today’s C55x wireless handset processors are fabricated in a 90 nm process, while the C55x+ chips will be fabricated in 65 nm.

The C55x+ also achieves a higher clock speed by using a longer pipeline: Its pipeline is four stages longer than the C55x pipeline. The long C55x+ pipeline has its drawbacks: BDTI found that the scheduling rules associated with the pipeline make it difficult to hand-optimized assembly code for the C55x+.

The C55x+ also offers a higher level of parallelism than the C55x. For example, the C55x+ has two ALUs instead of the single ALU found on the C55x. In addition, the C55x+ can load up to 64 bits of data per cycle, compared to a maximum load bandwidth of 48 bits per cycle on the C55x.

The C55x+ also offers a greater degree of flexibility than the C55x. For example, both the C55x+ and the C55x can issue up to two instructions per cycle, but the C55x+ supports about three times as many instruction combinations. The greater flexibility helps boost the performance of the C55x+, and it makes the processor a better compiler target.

In terms of speed, the C55x+ compares favorably to competitors’ current wireless handset processors, such as those from Freescale and Analog Devices. For example, the 500 MHz C55x+ is about 10% faster than the 250 MHz SC140 used by Freescale, and about two times faster than the 260 MHz Blackfin used by Analog Devices.

Of course, these competitors are likely to introduce faster chips before the C55x+ enters production. Freescale and Analog Devices currently fabricate their chips in a 90 nm process, but they may move to a 65 nm process in the near future. These competitors may also introduce new architectures. For example, Freescale could adopt the SC3000 architecture, which is expected to run at much higher clock speeds than the SC140. (For more on the SC3000, see the November 2005 edition of Inside DSP.)

It is also notable that that the C55x+ has to run at twice the clock rate of the SC140 in order to achieve a 10% speed advantage. This difference in clock rates suggests that the SC140 may offer better energy efficiency. Unfortunately, BDTI could not obtain enough data to determine if this is the case. Similarly, chip vendors generally do not publicly disclose the pricing of their handset chips. As a result, BDTI cannot determine the cost-effectiveness of the C55x+.

In addition to boosting performance, TI also added features to the C55x+ that make it a better target for control-oriented tasks. For example, TI added a memory-management unit (MMU), branch prediction, and support for byte addressing. TI added these features to enable “single-core modem” designs. Today, most wireless handset chips include two processor cores for the “baseband” (modem) function: a DSP core for the physical-layer processing, and an ARM core for the protocol stack. The control-oriented features in the C55x+ make it possible to run both types of tasks on the C55x+, eliminating the need for an ARM core. It is worth noting that TI is not the first to take this approach. At least one competitor—namely, Freescale—has already taken this approach.

Overall, the C55x+ is a major upgrade to the C55x. The C55x+ should help TI defend its leading market share in wireless handset chips. However, the C55x+ faces strong competition. With the market for wireless handsets showing no signs of slowing, it is certain that the battle will be well worth watching.

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