Tools

Jeff Bier’s Impulse Response—DSP Vendors Need Multi-Core Tools Strategy

There’s been a lot of press lately about start-up companies offering multi-core DSP chips.  What’s less widely discussed is that large, established DSP chip vendors have been offering multi-core DSP chips for years.  These chips have been popular in “channelized” applications where workload partitioning is fairly straightforward. But as multi-core DSPs move into a wider range of applications—and as the number of cores per chip grows—partitioning workloads among cores is becoming much Read more...

Plurality’s Hypercore Joins the Multi-Core Fray

There’s no shortage of startup companies with massively parallel processor architectures targeting high-performance signal processing applications, but Israel-based newcomer Plurality (www.plurality.com) isn’t discouraged. The company recently introduced a new multi-core architecture, Hypercore, that can support from 16 to 256 RISC processors on a single chip. Plurality is betting that its patented “synchronizer/scheduler” hardware—which the company claims enables “the programmability of a Read more...

CEVA Unveils “Lite” Mobile Multimedia Platform

In March CEVA unveiled “Mobile-Media-Lite” (MMLite), a family of multimedia processing solutions comprising licensable silicon IP and software. The family is aimed at low-end multimedia-enabled devices such as mobile TV players, portable multimedia players, and multimedia phones. CEVA also announced the first family member, the MM2200, a single-processor multimedia engine. CEVA’s intent is to provide highly integrated, application-optimized solutions; the company states that the MM2200 is Read more...

Xilinx Spartan gets DSP

In recent years, FPGA vendors have been aggressively pursuing high-performance signal processing applications. This month Xilinx broadened its target DSP markets by announcing a new lower-cost DSP-oriented FPGA family, Spartan-3A DSP. Spartan-3A DSP FPGAs are intended to provide better DSP performance than other Spartan devices while being less expensive than Xilinx’s high-performance Virtex-4 and Virtex-5 families. The new chip family targets cost-sensitive applications with high computational Read more...

Stretch Announces Second-generation Software Configurable Processor

On March 5, Stretch, Inc. announced its second-generation software configurable processor family, the S6000, and two initial chips. With this offering—its first since the appointment last year of a new CEO—Stretch is mainly targeting video surveillance, video broadcast, and WiMAX basestation applications. The S6000, like the previous-generation S5000 family, is a RISC processor which incorporates a reconfigurable compute fabric within its datapath. The fabric (which Stretch calls ISEF) Read more...

BDTI Evaluates TI’s DaVinci Evaluation Module

Last month BDTI published a white paper detailing the results of its analysis of Texas Instruments’ Digital Video Evaluation Module (DVEVM).  The DVEVM is one component of TI's “DaVinci” digital video platform, which also includes video-oriented chips, off-the-shelf multimedia codec software, development tools, and APIs.   BDTI's evaluation focuses on whether the DVEVM is straightforward to use, how well it supports application prototyping, and whether it provides system designers with enough Read more...

Jeff Bier’s Impulse Response—Efficiency Comes in Many Flavors

These days, there are so many start-ups developing programmable processors that it feels like we’re back in the “bubble” years, when anyone with a remotely viable processor design could secure venture funding. A pivotal question for the current crop of start-ups is whether to offer their processors as flexible, general-purpose chips, or as highly specialized, application-specific solutions. Should it be a jack-of-all-trades, or a master of one? If the processor is complex or the programming Read more...

Stream Processors Unveils Data-parallel Processor Architecture

Stream Processors, Inc. (SPI) this week unveiled its data-parallel processor architecture and announced two chips based on the architecture.  According to SPI, its architecture is optimized for compute-intensive embedded applications which exhibit a high degree of data parallelism, such as video and imaging.  SPI believes that cost-performance and developer productivity advantages will enable its chips to compete successfully against FPGAs, high-end DSPs, and ASICs in these applications. Read more...

Texas Instruments Announces Multi-core Baseband Processor

In December Texas Instruments announced the TCI6487 multi-core baseband processor. The device will be manufactured in a 65 nm process and is intended mainly for GSM, TD-SCDMA and WiMAX basestation applications. The TCI6487 features three TMS320C64x+ DSP cores running at 1 GHz. In comparison, its predecessor, the TCI6482, featured a single 1 GHz ‘64x+ core. TI has also added an antenna interface supporting OBSAI and CPRI protocols. DSP cores in the TCI6487 communicate with each other and Read more...

Getting Better DSP Code Out of Your Compiler

Compiling digital signal processing application code is not a push-button process—at least, not unless you're willing to settle for inefficient code. Signal processing algorithms (and the processors commonly used to run them) have specialized characteristics, and compilers usually can't generate efficient code for them without some level of programmer intervention. Learning how to coax efficient signal processing object code out of a compiler is an important skill, and can reduce (or eliminate Read more...